Author: john

Some Time with the Arty Arix-7 35T Digilent Board

So I wanted to implement a simple, stripped down version of the open-source lightweight IP stack “lwIP” (https://savannah.nongnu.org/projects/lwip/) inside my LabVIEW FPGA project that I can handle TCP and UDP data streams. I do not have a lot of experience with this, and I found that building such a project inside Vivado would take around […]

More Code Posted to Github

So I have figured out how to use the MicroBlaze Core with an AXI-Stream FIFO, and I have also figured out how to export a project from Vivado by using the Vivado “Write Project TCL” option. See the following project: https://github.com/JohnStratoudakis/LabVIEW_Fpga/tree/master/06_MicroBlaze/04_lwIP_Ex You have to re-generate the Vivado Project and create a new SDK workspace in […]

New Code Added to GitHub – MicroBlaze MCS, IO Bus and LabVIEW

I just uploaded some code to GitHub that is a full demonstration on how to use LabVIEW FPGA 2017, the MicroBlaze MCS core and the IO Bus that is attached to the MicroBlaze MCS. Clone the following repository: https://github.com/JohnStratoudakis/LabVIEW_Fpga/tree/master/05_MicroBlaze_Mcs/02_MicroBlaze_Mcs_IO_Bus and open the LabVIEW project: https://github.com/JohnStratoudakis/LabVIEW_Fpga/blob/master/05_MicroBlaze_Mcs/02_MicroBlaze_Mcs_IO_Bus/02_MicroBlaze_Mcs_IO_Bus.lvproj Look at the Vivado 2015.4 project: https://github.com/JohnStratoudakis/LabVIEW_Fpga/blob/master/05_MicroBlaze_Mcs/02_MicroBlaze_Mcs_IO_Bus/MicroBlaze_Mcs_IO_Bus/MicroBlaze_Mcs_IO_Bus.xpr And finally, using […]

How to Use the Microblaze Micro Controller System from LabVIEW

The MicroBlaze Micro Controller Syste (MCS) is a soft-core processor that can be customized and placed inside the fabric of your FPGA.  The uses of this are limitless. Requirements: LabVIEW 2017 http://www.ni.com/download/labview-development-system-2017/6679/en/ LabVIEW 2017 FPGA Module http://www.ni.com/download/labview-fpga-module-2017/6635/en/ LabVIEW 2017 FPGA Module Xilinx Compilation Tools for Vivado 2015.4 http://www.ni.com/download/labview-fpga-module-2017/6634/en/ Xilinx Software Development Kit version 2015.4 https://www.xilinx.com/products/design-tools/embedded-software/sdk.html […]

Filter Market Data Messages in an FPGA – part 3

Filter Market Data Messages in an FPGA – part 3 Note: Skip directly to GitHub.com to download the source code by following this link: https://github.com/fpganow/MarketData System Requirements: LabVIEW 2016 LabVIEW 2016 FPGA Module http://www.ni.com/labview/ This post will cover the next iteration of implementing an OrderBook inside an FPGA that is based on a NASDAQ ITCH […]

Filter Market Data Messages in an FPGA – part 2

Skip directly to the source code on Github.com here: https://github.com/JohnStratoudakis/LabVIEW_Fpga/tree/master/MarketData/MarketData_01 So what now.  We know what a NASDAQ ITCH 4.1 Market Data Message looks like.  The format is very simple, there is some – yes – ASCII data in the message format, and all messages are preceded by the message length.  Message length preceding the […]

Filter Market Data Messages in an FPGA – part 1

So I went to NASDAQs ftp site and downloaded the entire ITCH feed for November 9th, 2013.  The file was large – 319MB compressed, and you can download it yourself from here: ftp://emi.nasdaq.com/ITCH/11092013.NASDAQ_ITCH41.gz. NASDAQ has a very simple document describing the specification here: http://nasdaqtrader.com/content/technicalsupport/specifications/dataproducts/NQTV-ITCH-V4_1.pdf I skimmed over the specification to get an idea of how Market […]

From Trump to Profit

I am sure that every single trader gets nervous whenever Trump speaks.  If he says “wall” they have to go short the Mexican Peso, if he talks about Obamacare or the “Unaffordable Care Act”, they have to short Healthcare stocks.  During his first news conference on Thursday, January 11th, 2017, he went a step further […]