{"id":1366,"date":"2021-03-22T02:50:18","date_gmt":"2021-03-22T02:50:18","guid":{"rendered":"https:\/\/fpganow.com\/?page_id=1366"},"modified":"2022-01-16T17:11:36","modified_gmt":"2022-01-16T17:11:36","slug":"fpga-order-book","status":"publish","type":"page","link":"https:\/\/fpganow.com\/index.php\/fpga-order-book\/","title":{"rendered":"FPGA OrderBook"},"content":{"rendered":"\n<p>I am working on a 5-part series for how to turn your existing FPGA Board into an OrderBook, that uses an FPGA Accelerated Network card, or a &#8216;Smart-NIC&#8217; that will parse and normalize multiple Market Data Feeds and maintain an order book.<\/p>\n<p><em><strong>Note:<\/strong> Part 2 is available now, but it includes all the code\/IP for Part 1, I just did not get around to documenting part 1.\u00a0 I will make some nice documentation and test simulations for Part 1, and then I will get to Part 4.<\/em><\/p>\n<p>Here is a High-Level Diagram of the entire system:<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2021\/03\/High_Level-Simple.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-1401\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2021\/03\/High_Level-Simple.png\" alt=\"\" width=\"737\" height=\"248\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2021\/03\/High_Level-Simple.png 737w, https:\/\/fpganow.com\/wp-content\/uploads\/2021\/03\/High_Level-Simple-300x101.png 300w\" sizes=\"auto, (max-width: 737px) 100vw, 737px\" \/><\/a><\/p>\n<p>Each of the following pages will go over a specific portion of this system.<\/p>\n<p>\u00a0<\/p>\n<h2><strong>Part 1: Udp\/Ip Parser<\/strong><\/h2>\n<p>This part will go over how I used the LabVIEW FPGA Network library to listen on a specific MAC address, IP Address, and port to retrieve UDP data.<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2021\/05\/Part-1-Udp.Ip_.Parser.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-1413\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2021\/05\/Part-1-Udp.Ip_.Parser.png\" alt=\"\" width=\"548\" height=\"87\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2021\/05\/Part-1-Udp.Ip_.Parser.png 548w, https:\/\/fpganow.com\/wp-content\/uploads\/2021\/05\/Part-1-Udp.Ip_.Parser-300x48.png 300w\" sizes=\"auto, (max-width: 548px) 100vw, 548px\" \/><\/a><\/p>\n<p>\u00a0<\/p>\n<h2><a href=\"https:\/\/fpganow.com\/index.php\/parse-bats-messages-in-an-fpga\/\"><strong>Part 2: BATS PITCH Parser\/Normalizer<\/strong><\/a><\/h2>\n<p>This part I show how I took the raw UDP payload from step 1 and parse each BATS PITCH message and send a normalized format out, which in part 4 is wired to an OrderBook.<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2021\/05\/Part-2-BATS.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-1409\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2021\/05\/Part-2-BATS.png\" alt=\"\" width=\"795\" height=\"93\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2021\/05\/Part-2-BATS.png 795w, https:\/\/fpganow.com\/wp-content\/uploads\/2021\/05\/Part-2-BATS-300x35.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2021\/05\/Part-2-BATS-768x90.png 768w\" sizes=\"auto, (max-width: 795px) 100vw, 795px\" \/><\/a><\/p>\n<h2><strong>Part 3: NASDAQ ITCH Parser\/Normalizer<\/strong><\/h2>\n<p>Same thing as part 2, but this time I take NASDAQ messages and parse\/normalize them so that a combined OrderBook can be created.<\/p>\n<p>\u00a0<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2021\/05\/Part-3-NASDAQ.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-1410\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2021\/05\/Part-3-NASDAQ.png\" alt=\"\" width=\"838\" height=\"100\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2021\/05\/Part-3-NASDAQ.png 838w, https:\/\/fpganow.com\/wp-content\/uploads\/2021\/05\/Part-3-NASDAQ-300x36.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2021\/05\/Part-3-NASDAQ-768x92.png 768w\" sizes=\"auto, (max-width: 838px) 100vw, 838px\" \/><\/a><\/p>\n<h2><a href=\"https:\/\/fpganow.com\/index.php\/part-4-order-book\/\"><strong>Part 4: Order Book<\/strong><\/a><\/h2>\n<p>The BATS Normalizer and the NASDAQ Normalizer send Order Book &#8216;commands&#8217;, these commands add\/edit\/remove entries in the Order Book.\u00a0 A User App is a consumer of this data, so the User App will send a different set of commands, which right now are &#8216;Get.Top&#8217;, and &#8216;Get.All&#8217;.\u00a0 These commands come with a Symbol ID to tell the Order Book to get the best buy\/sell or the entire Order Book for a specific symbol.\u00a0 Finally an Arbitrator is placed in the middle to handle one or more<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2021\/05\/Part-4-OrderBook.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-1411\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2021\/05\/Part-4-OrderBook.png\" alt=\"\" width=\"594\" height=\"381\" \/><\/a><\/p>\n<h2><strong>Part 5: Application<\/strong><\/h2>\n<p>This part will put everything together and show how to create an application that communicates with a host (.exe\/binary) on a Windows\/Linux system &#8211; or to another FPGA IP<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2021\/05\/Part-5-Application.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-1412\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2021\/05\/Part-5-Application.png\" alt=\"\" width=\"291\" height=\"256\" \/><\/a>\u00a0<\/p>\n","protected":false},"excerpt":{"rendered":"<p>I am working on a 5-part series for how to turn your existing FPGA Board into an OrderBook, that uses an FPGA Accelerated Network card, or a &#8216;Smart-NIC&#8217; that will parse and normalize multiple Market Data Feeds and maintain an order book. Note: Part 2 is available now, but it includes all the code\/IP for &#8230; <a title=\"FPGA OrderBook\" class=\"read-more\" href=\"https:\/\/fpganow.com\/index.php\/fpga-order-book\/\" aria-label=\"Read more about FPGA OrderBook\">Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","footnotes":""},"class_list":["post-1366","page","type-page","status-publish"],"_links":{"self":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/pages\/1366","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/comments?post=1366"}],"version-history":[{"count":9,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/pages\/1366\/revisions"}],"predecessor-version":[{"id":19858,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/pages\/1366\/revisions\/19858"}],"wp:attachment":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/media?parent=1366"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}