{"id":19917,"date":"2025-12-22T14:12:41","date_gmt":"2025-12-22T14:12:41","guid":{"rendered":"http:\/\/localhost:8200\/?page_id=19917"},"modified":"2025-12-26T22:24:50","modified_gmt":"2025-12-26T22:24:50","slug":"home","status":"publish","type":"page","link":"https:\/\/fpganow.com\/","title":{"rendered":"fpganow.com"},"content":{"rendered":"\n\n<div class=\"wp-block-coblocks-posts is-style-stacked\"><div class=\"wp-block-coblocks-posts__inner has-columns has-2-columns has-responsive-columns has-square-image\"><div class=\"wp-block-coblocks-posts__item\"><div class=\"wp-block-coblocks-posts__content flex-start\"><time datetime=\"\" class=\"wp-block-coblocks-posts__date\">March 5, 2026<\/time><a href=\"https:\/\/fpganow.com\/index.php\/2026\/03\/05\/labview-fpga-on-amd-versal-yes\/\" alt=\"LabVIEW FPGA on AMD Versal? Yes\">LabVIEW FPGA on AMD Versal? Yes<\/a><div class=\"wp-block-coblocks-posts__excerpt\">LabVIEW FPGA has an IP Export tool that you can use to bring vi&#039;s from LabVIEW in to your custom design in Vivado.\u00a0 One constraint is that you can only use LabVIEW FPGA primitives, or put another way &#8211; logic that stays inside the FPGA, meaning you cannot write to DRAM or access some other IO pins on the NI board you are developing your LabVIEW FPGA IP &hellip; <\/div><\/div><\/div><div class=\"wp-block-coblocks-posts__item\"><div class=\"wp-block-coblocks-posts__content flex-start\"><time datetime=\"\" class=\"wp-block-coblocks-posts__date\">January 1, 2026<\/time><a href=\"https:\/\/fpganow.com\/index.php\/2026\/01\/01\/end-of-year-start-of-year\/\" alt=\"End of Year, Start of Year\">End of Year, Start of Year<\/a><div class=\"wp-block-coblocks-posts__excerpt\">I normally do not like the idea of New Years Resolutions as I think that every day is Day One of any plan, not January 1st of the next year.\u00a0 But it just so coincides that I have freed up some time to be able to spend more time on FPGANow.com again.\u00a0 So I went ahead and removed the menus at the top and simplified this site with &hellip; <\/div><\/div><\/div><div class=\"wp-block-coblocks-posts__item\"><div class=\"wp-block-coblocks-posts__content flex-start\"><time datetime=\"\" class=\"wp-block-coblocks-posts__date\">October 17, 2021<\/time><a href=\"https:\/\/fpganow.com\/index.php\/2021\/10\/17\/part-4-orderbook-now-published\/\" alt=\"Part 4 &#8211; OrderBook Now Published\">Part 4 &#8211; OrderBook Now Published<\/a><div class=\"wp-block-coblocks-posts__excerpt\">Part 4 of the Smart FPGA Nic, dealing with the OrderBook has been published. Go here to see more: https:\/\/fpganow.com\/index.php\/part-4-order-book\/ Related source code: https:\/\/github.com\/fpganow\/arty_bats\/tree\/main\/labview\/arty\/orderbook As I make updates to the code, mainly to make it prettier and easier for others to follow, I will make new a post for each change detailing all changes. \u00a0<\/div><\/div><\/div><div class=\"wp-block-coblocks-posts__item\"><div class=\"wp-block-coblocks-posts__content flex-start\"><time datetime=\"\" class=\"wp-block-coblocks-posts__date\">March 22, 2021<\/time><a href=\"https:\/\/fpganow.com\/index.php\/2021\/03\/22\/how-to-parse-bats-market-data-messages\/\" alt=\"How to Parse BATS Market Data Messages\">How to Parse BATS Market Data Messages<\/a><div class=\"wp-block-coblocks-posts__excerpt\">I just created a &#039;Page&#039; as opposed to a WordPress &#039;Post&#039; documenting how I was able to parse BATS Market Data messages. This new style or format will be much better than my writing multiples posts.\u00a0 Easier for the reader to find, and easier for me to find and to update an article. Anyway, look above, under the &quot;SMART &#039;FPGA-NIC&#039;&quot; menu above to find Part 2: Parse BATS &hellip; <\/div><\/div><\/div><div class=\"wp-block-coblocks-posts__item\"><div class=\"wp-block-coblocks-posts__content flex-start\"><time datetime=\"\" class=\"wp-block-coblocks-posts__date\">February 20, 2021<\/time><a href=\"https:\/\/fpganow.com\/index.php\/2021\/02\/20\/xilinx-vivado-and-source-control\/\" alt=\"Xilinx Vivado and Source Control\">Xilinx Vivado and Source Control<\/a><div class=\"wp-block-coblocks-posts__excerpt\">Related Source Repository: https:\/\/github.com\/fpganow\/vivado_scm Xilinx Vivado does not come with built-in source control.&nbsp; If you are a Visual Studio user, or a IntelliJ IDEA or eclipse user, you may be familiar with using some sort of IDE-related source code control. Vivado has a different paradigm for source control: Export commands to re-generate the project as a tcl script. Add tcl and all related files to source-control After I &hellip; <\/div><\/div><\/div><div class=\"wp-block-coblocks-posts__item\"><div class=\"wp-block-coblocks-posts__content flex-start\"><time datetime=\"\" class=\"wp-block-coblocks-posts__date\">February 19, 2021<\/time><a href=\"https:\/\/fpganow.com\/index.php\/2021\/02\/19\/dealing-with-the-vivado-drc-inbb-3-black-box-instances-issue\/\" alt=\"Dealing with the Vivado [DRC INBB-3]&#8217; Black Box Instances&#8217; issue\">Dealing with the Vivado [DRC INBB-3]&#8217; Black Box Instances&#8217; issue<\/a><div class=\"wp-block-coblocks-posts__excerpt\">So my workflow is as follows: Create IP in NI LabVIEW FPGA Export via FPGA IP Export Tool Creates a VHDL wrapper (.vhd) Places IP in Design Checkpoint (.dcp) file Open my Vivado Block Design Use or update the VHDL wrapper that uses the Design Checkpoint Synthesis, Implementation, and Run The NI LabVIEW FPGA IP Export utility provides you with 2 files, a design checkpoint and a wrapper &hellip; <\/div><\/div><\/div><div class=\"wp-block-coblocks-posts__item\"><div class=\"wp-block-coblocks-posts__content flex-start\"><time datetime=\"\" class=\"wp-block-coblocks-posts__date\">February 6, 2021<\/time><a href=\"https:\/\/fpganow.com\/index.php\/2021\/02\/06\/okay-parsing-udp-in-labview-fpga-works\/\" alt=\"Okay, Parsing UDP in LabVIEW FPGA Works\">Okay, Parsing UDP in LabVIEW FPGA Works<\/a><div class=\"wp-block-coblocks-posts__excerpt\">I got something working &#8211; with live hardware plugged in to my network. I used the larger version of the Arty Artix-7 board, which cost $250 USD, and made my own custom reader for the LabVIEW FPGA Network library.\u00a0 I did not implement network writing features, nor do anything with the payload.\u00a0 Nevertheless, this is a Proof-of-Concept and can be used to make a nice FPGA accelerated network &hellip; <\/div><\/div><\/div><div class=\"wp-block-coblocks-posts__item\"><div class=\"wp-block-coblocks-posts__content flex-start\"><time datetime=\"\" class=\"wp-block-coblocks-posts__date\">November 19, 2020<\/time><a href=\"https:\/\/fpganow.com\/index.php\/2020\/11\/19\/vivado-error-opt-31-67-and-how-i-fixed-it\/\" alt=\"Vivado Error [Opt 31-67], and How I Fixed It.\">Vivado Error [Opt 31-67], and How I Fixed It.<\/a><div class=\"wp-block-coblocks-posts__excerpt\">So I am dealing with the following scenarios: Scenario 1 &#8211; Genesys Zynq with SYZYGY SFP I have the Genesys Zynq UltraScale+ MPSoC 3EG board that does not provide direct access to the PHY pins, but has a SYZYGY port that I have plugged in to the SZG-DUALSFP module with an SFP connector. Scenario 2 &#8211; Arty A7 Artix-7 with 10\/100 Mbit PHY I have the Arty A7 &hellip; <\/div><\/div><\/div><div class=\"wp-block-coblocks-posts__item\"><div class=\"wp-block-coblocks-posts__content flex-start\"><time datetime=\"\" class=\"wp-block-coblocks-posts__date\">November 11, 2020<\/time><a href=\"https:\/\/fpganow.com\/index.php\/2020\/11\/11\/plans-using-arty-artix-7\/\" alt=\"Plans Using Arty Artix-7\">Plans Using Arty Artix-7<\/a><div class=\"wp-block-coblocks-posts__excerpt\">Here is the new plan: Step 1 &#8211; Create a design using a MicroBlaze processing system, enable a UART connection and listen on an AXI FIFO and dump packets to the screen as they are received in chunks of X bytes. Step 2 &#8211; Insert some LabVIEW FPGA code to send one packet of data every second. Step 3 &#8211; Replace this LabVIEW FPGA code to listen to &hellip; <\/div><\/div><\/div><div class=\"wp-block-coblocks-posts__item\"><div class=\"wp-block-coblocks-posts__content flex-start\"><time datetime=\"\" class=\"wp-block-coblocks-posts__date\">November 9, 2020<\/time><a href=\"https:\/\/fpganow.com\/index.php\/2020\/11\/09\/and-another-alternative\/\" alt=\"And Another Alternative\">And Another Alternative<\/a><div class=\"wp-block-coblocks-posts__excerpt\">I no longer have to look into figuring out how to code up or wire up the SZG-DUALSFP daughter board to the Digilent Genesys Zynq UltraScale MPSoC+ board. Why? Because I have a really old board that cost only $99 dollars that gives me direct access to the pins of an old 10\/100 MBit PHY! That&#039;s the Arty Artix-35T mini board! Anyway&#8230; I found a corresponding NI &quot;no &hellip; <\/div><\/div><\/div><div class=\"wp-block-coblocks-posts__item\"><div class=\"wp-block-coblocks-posts__content flex-start\"><time datetime=\"\" class=\"wp-block-coblocks-posts__date\">November 8, 2020<\/time><a href=\"https:\/\/fpganow.com\/index.php\/2020\/11\/08\/rebuilding-genesys-zynq-ultrascale-mpsoc-out-of-box-demo\/\" alt=\"Rebuilding Genesys Zynq UltraScale MPSoC+ Out of Box Demo\">Rebuilding Genesys Zynq UltraScale MPSoC+ Out of Box Demo<\/a><div class=\"wp-block-coblocks-posts__excerpt\">So I spent some time to rebuild the out-of-box demo for the Genesys Zynq UltraScale MPSoC+ board.\u00a0 Not everything worked for me right away, so I made this post to include all the things I did to get it to work.: My system: Windows 10 Windows Subsystem for Linux 2 Ubuntu 18.04 (&lt;= Ubuntu 20 does not work unless you make a lot of changes) References: Schematics https:\/\/reference.digilentinc.com\/_media\/reference\/programmable-logic\/genesys-zu\/genesys_zu-3eg_sch_public.pdf &hellip; <\/div><\/div><\/div><div class=\"wp-block-coblocks-posts__item\"><div class=\"wp-block-coblocks-posts__content flex-start\"><time datetime=\"\" class=\"wp-block-coblocks-posts__date\">October 28, 2020<\/time><a href=\"https:\/\/fpganow.com\/index.php\/2020\/10\/28\/szg-dualsfp-update\/\" alt=\"SZG-DUALSFP Update\">SZG-DUALSFP Update<\/a><div class=\"wp-block-coblocks-posts__excerpt\">I went to the Opal Kelly website again and noticed that there are a lot of menu options that I previously did not notice at the top menu. I found a sample board that uses their SZG-DUALSFP board: https:\/\/opalkelly.com\/products\/xem7320\/ So now I can read the documentation for this board and be on my way! I also had some fun reading the specification documents for the SYZYGY specification, the &hellip; <\/div><\/div><\/div><\/div><\/div>","protected":false},"excerpt":{"rendered":"","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","footnotes":""},"class_list":["post-19917","page","type-page","status-publish"],"_links":{"self":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/pages\/19917","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/comments?post=19917"}],"version-history":[{"count":6,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/pages\/19917\/revisions"}],"predecessor-version":[{"id":19958,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/pages\/19917\/revisions\/19958"}],"wp:attachment":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/media?parent=19917"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}