{"id":1054,"date":"2020-10-22T03:40:00","date_gmt":"2020-10-22T03:40:00","guid":{"rendered":"http:\/\/fpganow.com\/?p=1054"},"modified":"2020-10-26T12:55:28","modified_gmt":"2020-10-26T12:55:28","slug":"szg-dualsfp-howto","status":"publish","type":"post","link":"https:\/\/fpganow.com\/index.php\/2020\/10\/22\/szg-dualsfp-howto\/","title":{"rendered":"SZG-DUALSFP Howto?"},"content":{"rendered":"\n<p><span style=\"color: #000000;\">So I have the Genesys Zynq UltraScale + MPSoC board, I bought the SZG-DUALSFP from Opel Kelly, and I want to figure out how to wire this thing up.<\/span><\/p>\n<p><span style=\"color: #000000;\">What pin goes where? I dunno.\u00a0 I spent some time reading the SFP+ specification.\u00a0 Everything makes sense.\u00a0 Then I read through the SYZYGY specification.\u00a0 Again, things make sense.<\/span><\/p>\n<p><span style=\"color: #000000;\">So what does the interface look like? Anybody know?<\/span><\/p>\n<p><span style=\"color: #000000;\">One though is to look at a sample from a similar board that uses an FMC based SFP connector.<\/span><\/p>\n<p><span style=\"color: #000000;\">And then I was reminded of the book &#8220;How Would You Move Mount Fuji&#8221; &#8211; a book about interviewing at Microsoft.\u00a0 It included questions asked at Microsoft &#8211; including How Would You Move Mount Fuji.\u00a0 Rename it? How many dump trucks?\u00a0 All about out-of-the-box thinking.<\/span><\/p>\n<p><span style=\"color: #000000;\">Lesson? Who said I need to use this Genesys board.\u00a0 I may have to switch to a more expensive board that has an SFP connector integrated.\u00a0 Or maybe I should just look at a sample from such a board, and then everything will become clear.<\/span><\/p>\n<p><span style=\"color: #000000;\">I think I will go with the latest NetFPGA board.\u00a0 They seem to support the open-source community and Universities well.<\/span><\/p>\n<p><span style=\"color: #000000;\">References:<\/span><\/p>\n<ul>\n<li><a href=\"http:\/\/syzygyfpga.io\/wp-content\/uploads\/2019\/09\/Syzygy-Specification-V1p1.pdf\" target=\"_blank\" rel=\"noopener noreferrer\"><span style=\"color: #000000;\">http:\/\/syzygyfpga.io\/wp-content\/uploads\/2019\/09\/Syzygy-Specification-V1p1.pdf<\/span><\/a><\/li>\n<li><a href=\"https:\/\/docs.opalkelly.com\/display\/SZGPODS\/SZG-DUALSFP\" target=\"_blank\" rel=\"noopener noreferrer\"><span style=\"color: #000000;\">https:\/\/docs.opalkelly.com\/display\/SZGPODS\/SZG-DUALSFP<\/span><\/a><\/li>\n<li><a href=\"https:\/\/www.embedded.com\/syzygy-the-goldilocks-connection-standard-for-fpga-based-systems\/\" target=\"_blank\" rel=\"noopener noreferrer\"><span style=\"color: #000000;\">https:\/\/www.embedded.com\/syzygy-the-goldilocks-connection-standard-for-fpga-based-systems\/<\/span><\/a><\/li>\n<li><a href=\"https:\/\/www.10gtek.com\/templates\/wzten\/pdf\/SFF-8431-(SFP+%20MSA).pdf\" target=\"_blank\" rel=\"noopener noreferrer\"><span style=\"color: #000000;\">https:\/\/www.10gtek.com\/templates\/wzten\/pdf\/SFF-8431-(SFP+%20MSA).pdf<\/span><\/a><\/li>\n<li><a href=\"https:\/\/opalkelly.com\/products\/szg-dualsfp\/\" target=\"_blank\" rel=\"noopener noreferrer\"><span style=\"color: #000000;\">https:\/\/opalkelly.com\/products\/szg-dualsfp\/<\/span><\/a><\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>So I have the Genesys Zynq UltraScale + MPSoC board, I bought the SZG-DUALSFP from Opel Kelly, and I want to figure out how to wire this thing up. What pin goes where? I dunno.\u00a0 I spent some time reading the SFP+ specification.\u00a0 Everything makes sense.\u00a0 Then I read through the SYZYGY specification.\u00a0 Again, things &#8230; <a title=\"SZG-DUALSFP Howto?\" class=\"read-more\" href=\"https:\/\/fpganow.com\/index.php\/2020\/10\/22\/szg-dualsfp-howto\/\" aria-label=\"Read more about SZG-DUALSFP Howto?\">Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","footnotes":""},"categories":[1],"tags":[],"class_list":["post-1054","post","type-post","status-publish","format-standard","hentry","category-uncategorized","masonry-post","generate-columns","tablet-grid-50","mobile-grid-100","grid-parent","grid-50"],"_links":{"self":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/1054","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/comments?post=1054"}],"version-history":[{"count":5,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/1054\/revisions"}],"predecessor-version":[{"id":1080,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/1054\/revisions\/1080"}],"wp:attachment":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/media?parent=1054"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/categories?post=1054"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/tags?post=1054"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}