{"id":1056,"date":"2020-11-08T22:35:05","date_gmt":"2020-11-08T22:35:05","guid":{"rendered":"http:\/\/fpganow.com\/?p=1056"},"modified":"2020-11-08T22:36:35","modified_gmt":"2020-11-08T22:36:35","slug":"rebuilding-genesys-zynq-ultrascale-mpsoc-out-of-box-demo","status":"publish","type":"post","link":"https:\/\/fpganow.com\/index.php\/2020\/11\/08\/rebuilding-genesys-zynq-ultrascale-mpsoc-out-of-box-demo\/","title":{"rendered":"Rebuilding Genesys Zynq UltraScale MPSoC+ Out of Box Demo"},"content":{"rendered":"\n<p>So I spent some time to rebuild the out-of-box demo for the<a href=\"https:\/\/www.origin.xilinx.com\/products\/boards-and-kits\/1-18dv0nz.html\" target=\"_blank\" rel=\"noopener noreferrer\"> <strong>Genesys Zynq UltraScale MPSoC+<\/strong><\/a> board.\u00a0 Not everything worked for me right away, so I made this post to include all the things I did to get it to work.:<\/p>\n<h3><span style=\"text-decoration: underline;\"><strong><span style=\"text-decoration: underline;\">My system:<\/span><\/strong><\/span><\/h3>\n<ul>\n<li>Windows 10<\/li>\n<li>Windows Subsystem for Linux 2<\/li>\n<li>Ubuntu 18.04 (&lt;= Ubuntu 20 does not work unless you make a lot of changes)<\/li>\n<\/ul>\n<h3><span style=\"text-decoration: underline;\"><strong><span style=\"text-decoration: underline;\">References:<\/span><\/strong><\/span><\/h3>\n<ul>\n<li>Schematics\n<ul>\n<li><a href=\"https:\/\/reference.digilentinc.com\/_media\/reference\/programmable-logic\/genesys-zu\/genesys_zu-3eg_sch_public.pdf\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/reference.digilentinc.com\/_media\/reference\/programmable-logic\/genesys-zu\/genesys_zu-3eg_sch_public.pdf<\/a><\/li>\n<\/ul>\n<\/li>\n<li>Official Documentation from Digilent\n<ul>\n<li>Official Getting Started Guide on Digilent website\n<ul>\n<li><a href=\"https:\/\/reference.digilentinc.com\/reference\/programmable-logic\/genesys-zu\/getting-started\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/reference.digilentinc.com\/reference\/programmable-logic\/genesys-zu\/getting-started<\/a><\/li>\n<li><a href=\"https:\/\/reference.digilentinc.com\/reference\/programmable-logic\/genesys-zu\/start\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/reference.digilentinc.com\/reference\/programmable-logic\/genesys-zu\/start<\/a><\/li>\n<\/ul>\n<\/li>\n<li>Genesys Zynq UltraScale MPSoC+ Reference Manual\n<ul>\n<li><a href=\"https:\/\/reference.digilentinc.com\/reference\/programmable-logic\/genesys-zu\/reference-manual\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/reference.digilentinc.com\/reference\/programmable-logic\/genesys-zu\/reference-manual<\/a><\/li>\n<\/ul>\n<\/li>\n<li>Purchase Link\n<ul>\n<li><a href=\"https:\/\/store.digilentinc.com\/genesys-zu-zynq-ultrascale-mpsoc-development-board\/\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/store.digilentinc.com\/genesys-zu-zynq-ultrascale-mpsoc-development-board\/<\/a><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<li>PetaLinux Tools Documentation\n<ul>\n<li><a href=\"https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2018_3\/ug1144-petalinux-tools-reference-guide.pdf\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2018_3\/ug1144-petalinux-tools-reference-guide.pdf<\/a><\/li>\n<\/ul>\n<\/li>\n<li>Processing System 7 v5.,5 Documentation\n<ul>\n<li><a href=\"https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/processing_system7\/v5_5\/pg082-processing-system7.pdf\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/processing_system7\/v5_5\/pg082-processing-system7.pdf<\/a><\/li>\n<\/ul>\n<\/li>\n<li>Zynq UltraScale+ MPSoC Processing System Documentation\n<ul>\n<li><a href=\"https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/zynq_ultra_ps_e\/v3_0\/pg201-zynq-ultrascale-plus-processing-system.pdf\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/zynq_ultra_ps_e\/v3_0\/pg201-zynq-ultrascale-plus-processing-system.pdf<\/a><\/li>\n<\/ul>\n<\/li>\n<li>Cool Example to play Doom on this board\n<ul>\n<li><a href=\"https:\/\/github.com\/leos313\/DOOM_FPGA\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/github.com\/leos313\/DOOM_FPGA<\/a><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<h3><strong>These are comments generated after following this guide:<\/strong><\/h3>\n<ul>\n<li><a href=\"https:\/\/reference.digilentinc.com\/reference\/programmable-logic\/genesys-zu\/getting-started\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/reference.digilentinc.com\/reference\/programmable-logic\/genesys-zu\/getting-started<\/a><\/li>\n<\/ul>\n<h4>Run Out of Box Demo<\/h4>\n<p>I followed the instructions on the page linked above and everything worked and the instructions were very easy to follow.\u00a0 Some things to keep in mind:<\/p>\n<ul>\n<li>I used the wrong serial port and had to deal with some issues killing that Putty Window.<\/li>\n<li>Looks like <strong>sshd<\/strong> is not automatically configured\/turned on for the PetaLinux distribution.<\/li>\n<li>The default configuration mounts to root filesystem in RAM &#8211; aka &#8211; initramfs.\u00a0 So if you make any changes rebooting will not work.<\/li>\n<\/ul>\n<p>After connecting I noted my MAC address by running &#8216;ip a&#8217; as the tutorial mentioned and set up my router to always give it the same ip address.<\/p>\n<p>I then played around with setting some LEDs on and off by running the command:<\/p>\n<pre><em>for i in {0..4}; do uio-test -t led -i $i -v 1; done<\/em><\/pre>\n<p><span style=\"color: inherit; font-size: 23px; font-weight: 900;\"><br \/>Part 1 &#8211; Rebuilding the Out of Box Hardware Design<\/span><\/p>\n<h4>Step 1 &#8211; Create a directory for work<\/h4>\n<p>I used <strong>WSL 2<\/strong> running Ubuntu 18, and I created a directory for my work on my regular windows\/ntfs partition:<\/p>\n<pre><em>cd \/mnt\/c\/work<\/em><br \/><em>mkdir -p Genesys\/Rebuild<\/em><br \/><em>cd Genesys\/Rebuild<\/em><\/pre>\n<h4>Step 2 &#8211; Clone Hardware Design<\/h4>\n<p>Then I cloned the source code for the hardware design &#8211; making sure to get all submodules.\u00a0 Well, there is only one submodule, but that&#8217;s fine.<\/p>\n<pre><em>git clone --recurse git@github.com:Digilent\/Genesys-ZU-OOB-hw.git<\/em><\/pre>\n<p>(Browse the repository here:<a href=\"https:\/\/github.com\/Digilent\/Genesys-ZU-OOB-hw\" target=\"_blank\" rel=\"noopener noreferrer\"> https:\/\/github.com\/Digilent\/Genesys-ZU-OOB-hw<\/a>)<\/p>\n<p><span style=\"text-decoration: underline;\">Here are some notes about git and sub-modules:<\/span><\/p>\n<p>You can clone the code this way to get all sub-modules:<\/p>\n<pre><em>git clone --recurse &lt;git-url&gt;<\/em><\/pre>\n<p>but if you have already cloned the repository and want to get the submodules without re-cloning:<\/p>\n<pre><em>git submodule update --init --recursive<\/em><\/pre>\n<p>You can verify this by looking at the <em><strong>.gitmodules<\/strong><\/em> files in the root of the repository, it should look like this:<\/p>\n<pre><em>cat .gitmodules<br \/><\/em><br \/><em>[submodule \"repo\/vivado-library\"]<\/em><br \/><em>    path = repo\/vivado-library<\/em><br \/><em>    url = https:\/\/github.com\/Digilent\/vivado-library.git<\/em><br \/><em>    branch = master<\/em><\/pre>\n<p>And you can also verify the code was downloaded with:<\/p>\n<pre><em>ls -l repo\/vivado-library<\/em><\/pre>\n<p>Total space used after a fresh cloine with the sub-module: 148 Mebabytes<\/p>\n<h4>Step 3 &#8211; Start Vivado<\/h4>\n<p>In the Tcl Console (pronounced &#8216;tickle&#8217;) go to the directory where the Genesys-ZU-OOB-hw git repository has been cloned to:<\/p>\n<pre><em>cd C:\/work\/Genesys\/Rebuild\/Genesys-ZU-OOB-hw\/<\/em><\/pre>\n<p>(Vivado has some great auto-complete, just press tab)<\/p>\n<h4>Step 4 &#8211; Re-create Out-of-Box Project<\/h4>\n<p>Then source the create_project.tcl file.<\/p>\n<pre><em>source .\/proj\/create_project.tcl<\/em><\/pre>\n<h4><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-01-Full_Project_View.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-1121 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-01-Full_Project_View.png\" alt=\"\" width=\"1842\" height=\"1080\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-01-Full_Project_View.png 1842w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-01-Full_Project_View-300x176.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-01-Full_Project_View-1024x600.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-01-Full_Project_View-768x450.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-01-Full_Project_View-1536x901.png 1536w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-01-Full_Project_View-1200x704.png 1200w\" sizes=\"auto, (max-width: 1842px) 100vw, 1842px\" \/><\/a><\/h4>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-02-Zoomed_In_View.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-1124 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-02-Zoomed_In_View.png\" alt=\"\" width=\"1842\" height=\"1080\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-02-Zoomed_In_View.png 1842w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-02-Zoomed_In_View-300x176.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-02-Zoomed_In_View-1024x600.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-02-Zoomed_In_View-768x450.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-02-Zoomed_In_View-1536x901.png 1536w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-02-Zoomed_In_View-1200x704.png 1200w\" sizes=\"auto, (max-width: 1842px) 100vw, 1842px\" \/><\/a><\/p>\n<h4>Step 5 &#8211; Build the Vivado Project<\/h4>\n<p>Just click <strong>&#8216;Generate Bitstream&#8217;<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-03-Click_Generate_Bitstream.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-1125 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-03-Click_Generate_Bitstream.png\" alt=\"\" width=\"321\" height=\"246\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-03-Click_Generate_Bitstream.png 321w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-03-Click_Generate_Bitstream-300x230.png 300w\" sizes=\"auto, (max-width: 321px) 100vw, 321px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-04-First_Warning_is_Fine.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-1126 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-04-First_Warning_is_Fine.png\" alt=\"\" width=\"606\" height=\"243\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-04-First_Warning_is_Fine.png 606w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-04-First_Warning_is_Fine-300x120.png 300w\" sizes=\"auto, (max-width: 606px) 100vw, 606px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-05-Final_Generate_Bitstream_Screen.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-1127 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-05-Final_Generate_Bitstream_Screen.png\" alt=\"\" width=\"557\" height=\"422\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-05-Final_Generate_Bitstream_Screen.png 557w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-05-Final_Generate_Bitstream_Screen-300x227.png 300w\" sizes=\"auto, (max-width: 557px) 100vw, 557px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-06-Generate_Bitstream_Running.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-1128 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-06-Generate_Bitstream_Running.png\" alt=\"\" width=\"742\" height=\"199\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-06-Generate_Bitstream_Running.png 742w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-06-Generate_Bitstream_Running-300x80.png 300w\" sizes=\"auto, (max-width: 742px) 100vw, 742px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-07-Final_Step.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-1129 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-07-Final_Step.png\" alt=\"\" width=\"421\" height=\"395\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-07-Final_Step.png 421w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-07-Final_Step-300x281.png 300w\" sizes=\"auto, (max-width: 421px) 100vw, 421px\" \/><\/a><\/p>\n<p>Took around 15 minutes on my computer, relatively modern desktop &#8211; around 6 years old.<\/p>\n<h4>Step 6 &#8211; Export Hardware<\/h4>\n<p>Click <em>File-&gt;Export-&gt;Export Hardware<\/em><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-08-Export_Hardware.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-1130 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-08-Export_Hardware.png\" alt=\"\" width=\"564\" height=\"673\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-08-Export_Hardware.png 564w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-08-Export_Hardware-251x300.png 251w\" sizes=\"auto, (max-width: 564px) 100vw, 564px\" \/><\/a><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-09-Include_Bitstream.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-1131 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-09-Include_Bitstream.png\" alt=\"\" width=\"503\" height=\"297\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-09-Include_Bitstream.png 503w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_1-09-Include_Bitstream-300x177.png 300w\" sizes=\"auto, (max-width: 503px) 100vw, 503px\" \/><\/a><\/p>\n<p>\u00a0<\/p>\n<p>Make sure you click <strong>&#8216;include bitstream&#8217;<\/strong><\/p>\n<p>The HDF file gets placed in the following directory:<\/p>\n<pre><em>C:\\work\\Genesys\\Rebuild\\Genesys-ZU-OOB-hw\\proj\\GZU3EG_demo.sdk<\/em><\/pre>\n<h3>Part 2 &#8211; Building the PetaLinux Image<\/h3>\n<p><span style=\"text-decoration: underline;\"><strong>Caveats:<\/strong><\/span><\/p>\n<ul>\n<li>Your distribution of Linux is important<\/li>\n<li>WSL (Windows Subsystem for Linux) is good, but not perfect, so be careful using it.<\/li>\n<\/ul>\n<p>I followed the instructions using WSL 2 using Ubuntu 18.04<\/p>\n<h4>Step 1 &#8211; Install PetaLinux for your Distribution<\/h4>\n<div>\n<div>References:<\/div>\n<ul>\n<li>See Xilinx UG1144 &#8211; PetaLinux Tools Documentation\n<ul>\n<li><a href=\"https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2018_3\/ug1144-petalinux-tools-reference-guide.pdf\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2018_3\/ug1144-petalinux-tools-reference-guide.pdf<\/a><\/li>\n<\/ul>\n<\/li>\n<li>See Xilinx ug976 &#8211; PetaLinux SDK User Guide\n<ul>\n<li><a href=\"https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/petalinux2013_10\/ug976-petalinux-installation.pdf\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/petalinux2013_10\/ug976-petalinux-installation.pdf<\/a><\/li>\n<\/ul>\n<\/li>\n<li>Download petalinux-v2019.1-final-install.run (7.2G)\n<ul>\n<li><a href=\"http:\/\/xilinx.com\/support\/download\/index.html\/content\/xilinx\/en\/downloadNav\/embedded-design-tools\/archive.html\" target=\"_blank\" rel=\"noopener noreferrer\">xilinx.com\/support\/download\/index.html\/content\/xilinx\/en\/downloadNav\/embedded-design-tools\/archive.html<\/a><\/li>\n<\/ul>\n<\/li>\n<li>Random PetaLinux Tutorial\n<ul>\n<li><a href=\"https:\/\/www.beyond-circuits.com\/wordpress\/tutorial\/tutorial23\/\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/www.beyond-circuits.com\/wordpress\/tutorial\/tutorial23\/<\/a><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/div>\n<p>I used Ubuntu 18.04 LTS running inside WSL 2 with the following updates:<\/p>\n<pre>sudo apt-get install -y gcc git make net-tools libncurses5-dev tftpd zlib1g-dev libssl-dev flex bison libselinux1 gnupg wget diffstat chrpath socat xterm autoconf libtool tar unzip texinfo zlib1g-dev gcc-multilib build-essential libsdl1.2-dev libglib2.0-dev\u00a0screen pax gzip python<\/pre>\n<div>\u00a0<\/div>\n<div><span style=\"text-decoration: underline;\">Troubleshooting:<\/span><\/div>\n<ul>\n<li>To install zlib1g:i386\n<ul>\n<li>sudo dpkg &#8211;add-architecture i386<\/li>\n<li>sudo apt-get update<\/li>\n<li>sudo apt-get install zlib1g:i386<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>Then make sure you copy the petalinux-v2019.1-final-install.run file to a non-<strong>NTFS<\/strong> mount:<\/p>\n<pre><em>sudo mkdir -p \/opt\/pkg\/petalinux\/2019.1<br \/><\/em><em>sudo chown john:john \/opt\/pkg\/petalinux\/2019.1<\/em><br \/><em>bash .\/petalinux-v2019.1-final-install.run \/opt\/pkg\/petalinux\/2019.1<\/em><\/pre>\n<h4>Step 2 &#8211; Source the Petalinux settings.sh file<\/h4>\n<pre><em>source \/opt\/pkg\/petalinux\/2019.1\/settings.sh<br \/><\/em>echo ${PETALINUX}<\/pre>\n<div>(Check for the PETALINUX environment variable to verify)<\/div>\n<div>echo ${PETALINUX}<\/div>\n<h4>Step 3 &#8211; Clone the Repository<\/h4>\n<pre>cd<br \/>mkdir -p Genesys\/Rebuild<br \/>cd Genesys\/Rebuild<br \/><em>git clone git@github.com:Digilent\/Genesys-ZU-OOB-os.git<\/em><br \/><em>cd Genesys-ZU-OOB-os<\/em><\/pre>\n<div>For this to work, you should not be on an NTFS partition, there are some\u00a0 issues with PetaLinux config tools.\u00a0 Hopefully by the time you read this these issues are fixed.<\/div>\n<h4>Step 4 &#8211; Configure PetaLinux<\/h4>\n<div>Go to where you have cloned the OS repository (Genesys-ZU-OOB-os) and run the command:<\/div>\n<div>\u00a0<\/div>\n<pre><em>petalinux-config --get-hw-description= \/mnt\/c\/work\/Genesys\/Rebuild\/Genesys-ZU-OOB-hw\/proj\/GZU3EG_demo.sdk\/<\/em><\/pre>\n<div>\u00a0<\/div>\n<div>Go through this DOS-like menu system and explore.\u00a0 I made the following changes:<\/div>\n<div>\u00a0<\/div>\n<div><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_2-05-Use_Defaults.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-1132 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_2-05-Use_Defaults.png\" alt=\"\" width=\"1755\" height=\"794\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_2-05-Use_Defaults.png 1755w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_2-05-Use_Defaults-300x136.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_2-05-Use_Defaults-1024x463.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_2-05-Use_Defaults-768x347.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_2-05-Use_Defaults-1536x695.png 1536w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/11\/Genesys_Rebuild_Part_2-05-Use_Defaults-1200x543.png 1200w\" sizes=\"auto, (max-width: 1755px) 100vw, 1755px\" \/><\/a><\/div>\n<div>\u00a0<\/div>\n<div><em><span style=\"text-decoration: underline;\"><strong>Write image to tftp root directory<\/strong><\/span><\/em><\/div>\n<ul>\n<li>Check TFTP destination\n<ul>\n<li>Image Packaging Configuration &#8212;&gt;\n<ul>\n<li>Check &#8220;Copy final images to tftpboot&#8221;<\/li>\n<li>Set tftpboot directory to \/mnt\/c\/TFTP-Root\/tftpboot\/zuca-3eg<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>Click Exit and let it run<del><\/del><\/p>\n<h5>Now configure the rootfs<\/h5>\n<pre>petalinux-config -c rootfs<\/pre>\n<ul>\n<li>Enable the ssh server\n<ul>\n<li>Filesystem Packages &#8212;&gt;\n<ul>\n<li>console &#8212;&gt;\n<ul>\n<li>network &#8212;&gt;\n<ul>\n<li>dropbear &#8212;&gt;\n<ul>\n<li>Enable dropbear<\/li>\n<\/ul>\n<\/li>\n<li>Admin &#8212;&gt;\n<ul>\n<li>sudo &#8212;&gt;\n<ul>\n<li>Enable sudo<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<h5>Create a Regular User:<\/h5>\n<div>\u00a0<\/div>\n<div>Edit the last line of the file:<\/div>\n<div>\u00a0<\/div>\n<pre><em>nano project-spec\/meta-plnx-generated\/recipes-core\/images\/petalinux-user-image.bb<\/em><\/pre>\n<div>\u00a0<\/div>\n<div>to contain:<\/div>\n<div>\u00a0<\/div>\n<div>\n<pre><em>EXTRA_USERS_PARAMS = \"usermod -P password root; useradd -P password john<strong>;<\/strong>\"<\/em><\/pre>\n<h4>Step 5 &#8211; Build the Image<\/h4>\n<\/div>\n<p>Just run petalinux-build<\/p>\n<pre>time petalinux-build<\/pre>\n<p>Took around 20 minutes on my Desktop with (24GB Ram and\u00a0 an Intel i7-4930K)<\/p>\n<h4>Step 6 &#8211; Package<\/h4>\n<pre class=\"code\">petalinux-package --boot --force --fsbl images\/linux\/zynqmp_fsbl.elf --fpga images\/linux\/system.bit --u-boot<\/pre>\n<h4>Step 7 &#8211; Copy Files to SD Card<\/h4>\n<p>Copy the <strong>BOOT.BIN<\/strong> and <strong>image.ub<\/strong> to the root of the SD Card &#8211; make sure the SD Card is FAT32 formatted.<\/p>\n<h4>Step 8 &#8211; Ssh to Genesys Board<\/h4>\n<p>I looked up and found the ip address of my board in my local router and it is <strong>&#8216;192.168.1.203&#8217;<\/strong>, I was able to ssh in as user john with password password.<\/p>\n<p>Now you can play around with the commands I mentioned at the start of this article.<\/p>\n<p>But what about the SYZYGY connector and 10 gigabit ethernet? If I just plug in it, how will I know if it is plugged in correctly and getting appropriate data?<\/p>\n<p>I don&#8217;t know.\u00a0 Perhaps I am better off spending my time proving out how you can use LabVIEW FPGA along with the IP Export utility to show how you can parse FIX messages using an FPGA, and without Verilog\/VHDL&#8230;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>So I spent some time to rebuild the out-of-box demo for the Genesys Zynq UltraScale MPSoC+ board.\u00a0 Not everything worked for me right away, so I made this post to include all the things I did to get it to work.: My system: Windows 10 Windows Subsystem for Linux 2 Ubuntu 18.04 (&lt;= Ubuntu 20 &#8230; <a title=\"Rebuilding Genesys Zynq UltraScale MPSoC+ Out of Box Demo\" class=\"read-more\" href=\"https:\/\/fpganow.com\/index.php\/2020\/11\/08\/rebuilding-genesys-zynq-ultrascale-mpsoc-out-of-box-demo\/\" aria-label=\"Read more about Rebuilding Genesys Zynq UltraScale MPSoC+ Out of Box Demo\">Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","footnotes":""},"categories":[1],"tags":[],"class_list":["post-1056","post","type-post","status-publish","format-standard","hentry","category-uncategorized","masonry-post","generate-columns","tablet-grid-50","mobile-grid-100","grid-parent","grid-50"],"_links":{"self":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/1056","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/comments?post=1056"}],"version-history":[{"count":58,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/1056\/revisions"}],"predecessor-version":[{"id":1134,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/1056\/revisions\/1134"}],"wp:attachment":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/media?parent=1056"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/categories?post=1056"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/tags?post=1056"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}