{"id":1136,"date":"2020-11-09T22:05:39","date_gmt":"2020-11-09T22:05:39","guid":{"rendered":"http:\/\/fpganow.com\/?p=1136"},"modified":"2020-11-09T22:05:39","modified_gmt":"2020-11-09T22:05:39","slug":"and-another-alternative","status":"publish","type":"post","link":"https:\/\/fpganow.com\/index.php\/2020\/11\/09\/and-another-alternative\/","title":{"rendered":"And Another Alternative"},"content":{"rendered":"\n<p>I no longer have to look into figuring out how to code up or wire up the SZG-DUALSFP daughter board to the Digilent Genesys Zynq UltraScale MPSoC+ board.<\/p>\n<p>Why? Because I have a really old board that cost only $99 dollars that gives me direct access to the pins of an old 10\/100 MBit PHY! That&#8217;s the Arty Artix-35T mini board!<\/p>\n<p>Anyway&#8230; I found a corresponding NI &#8220;no longer national instruments&#8221; board that targets the same family of FPGAs so I can get started.<\/p>\n<p>What that means is:<\/p>\n<ul>\n<li>Create a LabVIEW FPGA project that targets the CompactRIO 9053 board<\/li>\n<li>Use the LabVIEW FPGA IP Export the Netlist utility to get a design checkpoint<\/li>\n<li>Import that checkpoint in to my Arty project<\/li>\n<li>Generate an Arty Bitstream<\/li>\n<li>Load it to the FPGA<\/li>\n<li>Enjoy my FIX parsing code on this board with full ethernet connectivity.<\/li>\n<\/ul>\n<p>References:<\/p>\n<ul>\n<li>List of NI devices and the corresponding Xilinx FPGA that it uses:\n<ul>\n<li><a href=\"https:\/\/www.ni.com\/en-us\/support\/documentation\/supplemental\/18\/slices-on-an-fpga-chip.html\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/www.ni.com\/en-us\/support\/documentation\/supplemental\/18\/slices-on-an-fpga-chip.html<\/a><\/li>\n<\/ul>\n<\/li>\n<li>Arty A7-35T FPGA Development Board for Makers and Hobbyists\n<ul>\n<li><a href=\"https:\/\/store.digilentinc.com\/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists\/\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/store.digilentinc.com\/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists\/<\/a><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>However, the Genesys Board will still remain in my consciousness and will be a secondary hobbyist project that I will look into and play with whenever I am tired of the Arty board&#8230;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>I no longer have to look into figuring out how to code up or wire up the SZG-DUALSFP daughter board to the Digilent Genesys Zynq UltraScale MPSoC+ board. Why? Because I have a really old board that cost only $99 dollars that gives me direct access to the pins of an old 10\/100 MBit PHY! &#8230; <a title=\"And Another Alternative\" class=\"read-more\" href=\"https:\/\/fpganow.com\/index.php\/2020\/11\/09\/and-another-alternative\/\" aria-label=\"Read more about And Another Alternative\">Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","footnotes":""},"categories":[1],"tags":[],"class_list":["post-1136","post","type-post","status-publish","format-standard","hentry","category-uncategorized","masonry-post","generate-columns","tablet-grid-50","mobile-grid-100","grid-parent","grid-50"],"_links":{"self":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/1136","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/comments?post=1136"}],"version-history":[{"count":1,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/1136\/revisions"}],"predecessor-version":[{"id":1137,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/1136\/revisions\/1137"}],"wp:attachment":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/media?parent=1136"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/categories?post=1136"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/tags?post=1136"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}