{"id":1139,"date":"2020-11-11T18:19:51","date_gmt":"2020-11-11T18:19:51","guid":{"rendered":"http:\/\/fpganow.com\/?p=1139"},"modified":"2020-11-11T18:19:51","modified_gmt":"2020-11-11T18:19:51","slug":"plans-using-arty-artix-7","status":"publish","type":"post","link":"https:\/\/fpganow.com\/index.php\/2020\/11\/11\/plans-using-arty-artix-7\/","title":{"rendered":"Plans Using Arty Artix-7"},"content":{"rendered":"\n<p>Here is the new plan:<\/p>\n<p><strong>Step 1<\/strong> &#8211; Create a design using a MicroBlaze processing system, enable a UART connection and listen on an AXI FIFO and dump packets to the screen as they are received in chunks of X bytes.<\/p>\n<p><strong>Step 2<\/strong> &#8211; Insert some LabVIEW FPGA code to send one packet of data every second.<\/p>\n<p><strong>Step 3<\/strong> &#8211; Replace this LabVIEW FPGA code to listen to the MII Ethernet interface pins and to dump some data to the screen as before.<\/p>\n<p><strong>Step 4<\/strong> &#8211; Insert the LabVIEW FPGA UDP\/IP library that is included with LabVIEW<\/p>\n<p>Now if you want to follow along, get the board from here:<\/p>\n<p>http:\/\/store.digilentinc.com\/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists\/<\/p>\n<p>(I recommend getting the Arty A7-100T, but if you are a complete newbite, stick to the one that you find the most documentation for)<\/p>\n<p><span style=\"text-decoration: underline;\">Then follow these videos from FPGA Developer on YouTube:<\/span><\/p>\n<p><iframe loading=\"lazy\" title=\"Artix-7 Arty Base Project Part 1: Vivado design\" width=\"1200\" height=\"675\" src=\"https:\/\/www.youtube.com\/embed\/GyFTMwBjyOY?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture\" allowfullscreen><\/iframe><\/p>\n<p><iframe loading=\"lazy\" title=\"Artix-7 Arty Base Project Part 2: SDK\" width=\"1200\" height=\"675\" src=\"https:\/\/www.youtube.com\/embed\/8lrA5vrWgfo?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture\" allowfullscreen><\/iframe><\/p>\n<p><iframe loading=\"lazy\" title=\"Artix-7 Arty Base Project Part 3: PetaLinux\" width=\"1200\" height=\"675\" src=\"https:\/\/www.youtube.com\/embed\/8oIZxv3fJxs?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture\" allowfullscreen><\/iframe><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Here is the new plan: Step 1 &#8211; Create a design using a MicroBlaze processing system, enable a UART connection and listen on an AXI FIFO and dump packets to the screen as they are received in chunks of X bytes. Step 2 &#8211; Insert some LabVIEW FPGA code to send one packet of data &#8230; <a title=\"Plans Using Arty Artix-7\" class=\"read-more\" href=\"https:\/\/fpganow.com\/index.php\/2020\/11\/11\/plans-using-arty-artix-7\/\" aria-label=\"Read more about Plans Using Arty Artix-7\">Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","footnotes":""},"categories":[1],"tags":[],"class_list":["post-1139","post","type-post","status-publish","format-standard","hentry","category-uncategorized","masonry-post","generate-columns","tablet-grid-50","mobile-grid-100","grid-parent","grid-50"],"_links":{"self":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/1139","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/comments?post=1139"}],"version-history":[{"count":2,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/1139\/revisions"}],"predecessor-version":[{"id":1141,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/1139\/revisions\/1141"}],"wp:attachment":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/media?parent=1139"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/categories?post=1139"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/tags?post=1139"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}