{"id":1203,"date":"2021-02-19T14:39:43","date_gmt":"2021-02-19T14:39:43","guid":{"rendered":"http:\/\/fpganow.com\/?p=1203"},"modified":"2021-02-19T14:39:43","modified_gmt":"2021-02-19T14:39:43","slug":"dealing-with-the-vivado-drc-inbb-3-black-box-instances-issue","status":"publish","type":"post","link":"https:\/\/fpganow.com\/index.php\/2021\/02\/19\/dealing-with-the-vivado-drc-inbb-3-black-box-instances-issue\/","title":{"rendered":"Dealing with the Vivado [DRC INBB-3]&#8217; Black Box Instances&#8217; issue"},"content":{"rendered":"\n<p>So my workflow is as follows:<\/p>\n<ul>\n<li>Create IP in NI LabVIEW FPGA<\/li>\n<li>Export via FPGA IP Export Tool\n<ul>\n<li>Creates a VHDL wrapper (.vhd)<\/li>\n<li>Places IP in Design Checkpoint (.dcp) file<\/li>\n<\/ul>\n<\/li>\n<li>Open my Vivado Block Design<\/li>\n<li>Use or update the VHDL wrapper that uses the Design Checkpoint<\/li>\n<li>Synthesis, Implementation, and Run<\/li>\n<\/ul>\n<p>The NI LabVIEW FPGA IP Export utility provides you with 2 files, a design checkpoint and a wrapper file to use for instantiating your IP using VHDL.<\/p>\n<p>A wrapper file is a very simple vhdl file, it contains the following interface to your design:<\/p>\n<table style=\"border-collapse: collapse; width: 100%;\">\n<tbody>\n<tr>\n<td style=\"width: 100%;\">entity NiFpgaIPWrapper_fpga_top is<br>port (<br>&nbsp; &nbsp; &nbsp; &nbsp; reset : in std_logic;<br>&nbsp; &nbsp; &nbsp; &nbsp; enable_in : in std_logic;<br>&nbsp; &nbsp; &nbsp; &nbsp; enable_out : out std_logic;<br>&nbsp; &nbsp; &nbsp; &nbsp; enable_clr : in std_logic;<br>&nbsp; &nbsp; &nbsp; &nbsp; ctrlind_00_d : in std_logic_vector(0 downto 0);<br>&nbsp; &nbsp; &nbsp; &nbsp; ctrlind_01_d_latched : out std_logic_vector(0 downto 0);<br>&nbsp; &nbsp; &nbsp; &nbsp; ctrlind_02_c : in std_logic_vector(0 downto 0);<br>&nbsp; &nbsp; &nbsp; &nbsp; ctrlind_03_c_echo : out std_logic_vector(0 downto 0);<br>&nbsp; &nbsp; &nbsp; &nbsp; ctrlind_04_b : in std_logic_vector(0 downto 0);<br>&nbsp; &nbsp; &nbsp; &nbsp; ctrlind_05_a : in std_logic_vector(0 downto 0);<br>&nbsp; &nbsp; &nbsp; &nbsp; ctrlind_06_a_and_b : out std_logic_vector(0 downto 0);<br>&nbsp; &nbsp; &nbsp; &nbsp; ctrlind_07_a_or_b : out std_logic_vector(0 downto 0);<br>&nbsp; &nbsp; &nbsp; &nbsp; Clk40 : in std_logic<br>);<br>end NiFpgaIPWrapper_fpga_top;<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<hr>\n<p>However, in some situations using this method results in a problem, specifically Vivado will give a &#8216;Black Box Undefined error&#8217; during the opt_design step of the Implementation phase.<\/p>\n<table style=\"border-collapse: collapse; width: 100%;\">\n<tbody>\n<tr>\n<td style=\"width: 100%;\">&#8220;ERROR: [DRC INBB-3] &#8216;Black Box Instances: Cell &#8216;design_1_i\/&#8230;&#8217; of type &#8216;design_1_i\/&#8230;&#8217; has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.&#8221;<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>I have created a github.com repository where I have isolated this problem and make it very easy for someone to reproduce this error:<\/p>\n<p><a href=\"https:\/\/github.com\/fpganow\/black.box\" target=\"_blank\" rel=\"noopener\">https:\/\/github.com\/fpganow\/black.box<\/a><\/p>\n<p>But first, here is a screenshot of the error message: (left-clicking always opens in a new tab)<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2021\/02\/08-More_Details-1.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-1219 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2021\/02\/08-More_Details-1.png\" alt=\"\" width=\"1111\" height=\"409\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2021\/02\/08-More_Details-1.png 1111w, https:\/\/fpganow.com\/wp-content\/uploads\/2021\/02\/08-More_Details-1-300x110.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2021\/02\/08-More_Details-1-1024x377.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2021\/02\/08-More_Details-1-768x283.png 768w\" sizes=\"auto, (max-width: 1111px) 100vw, 1111px\" \/><\/a><\/p>\n\n\n\n<h2>Log output:<\/h2>\n<p><a href=\"https:\/\/github.com\/fpganow\/black.box\/blob\/main\/pictures\/black.box.instance.error.txt\" target=\"_blank\" rel=\"noopener\">https:\/\/github.com\/fpganow\/black.box\/blob\/main\/pictures\/black.box.instance.error.txt<\/a><\/p>\n<table style=\"border-collapse: collapse; width: 100%; height: 603px;\">\n<tbody>\n<tr style=\"height: 603px;\">\n<td style=\"width: 100%; height: 603px;\">\n<p><code>Starting DRC Task<\/code><br><code>INFO: [DRC 23-27] Running DRC with 2 threads<\/code><br><code>ERROR: [DRC INBB-3] Black Box Instances: Cell 'design_1_i\/my_wrapper_0\/U0\/ni_wrapper\/MyLabVIEWIP' of type 'design_1_my_wrapper_0_0_NiFpgaAG_fpga_top' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.<\/code><br><code>INFO: [Project 1-461] DRC finished with 1 Errors<\/code><br><code>INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.<\/code><br><code>ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.<\/code><\/p>\n<p><code>Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1760.746 ; gain = 0.000<\/code><br><code>INFO: [Common 17-83] Releasing license: Implementation<\/code><br><code>44 Infos, 8 Warnings, 1 Critical Warnings and 2 Errors encountered.<\/code><br><code>opt_design failed<\/code><br><code>ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.<\/code><\/p>\n<p><code>INFO: [Common 17-206] Exiting Vivado at Sun Feb 7 13:17:50 2021...<\/code><\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n\n<p>\u00a0<\/p>\n<p>\u00a0<\/p>\n<p>\u00a0<\/p>\n<p>And then I removed the .dcp file from my vivado project and used the generated .v file.<\/p>\n<p>Also, I chose to use -rename_top just to be sure that the IP I was exporting has the name I am expecting.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>So my workflow is as follows: Create IP in NI LabVIEW FPGA Export via FPGA IP Export Tool Creates a VHDL wrapper (.vhd) Places IP in Design Checkpoint (.dcp) file Open my Vivado Block Design Use or update the VHDL wrapper that uses the Design Checkpoint Synthesis, Implementation, and Run The NI LabVIEW FPGA IP &#8230; <a title=\"Dealing with the Vivado [DRC INBB-3]&#8217; Black Box Instances&#8217; issue\" class=\"read-more\" href=\"https:\/\/fpganow.com\/index.php\/2021\/02\/19\/dealing-with-the-vivado-drc-inbb-3-black-box-instances-issue\/\" aria-label=\"Read more about Dealing with the Vivado [DRC INBB-3]&#8217; Black Box Instances&#8217; issue\">Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","footnotes":""},"categories":[1],"tags":[],"class_list":["post-1203","post","type-post","status-publish","format-standard","hentry","category-uncategorized","masonry-post","generate-columns","tablet-grid-50","mobile-grid-100","grid-parent","grid-50"],"_links":{"self":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/1203","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/comments?post=1203"}],"version-history":[{"count":25,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/1203\/revisions"}],"predecessor-version":[{"id":1295,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/1203\/revisions\/1295"}],"wp:attachment":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/media?parent=1203"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/categories?post=1203"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/tags?post=1203"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}