{"id":126,"date":"2017-06-23T13:28:28","date_gmt":"2017-06-23T13:28:28","guid":{"rendered":"http:\/\/fpganow.com\/?p=126"},"modified":"2017-06-24T03:52:26","modified_gmt":"2017-06-24T03:52:26","slug":"how-to-use-the-microblaze-micro-controller-system-from-labview","status":"publish","type":"post","link":"https:\/\/fpganow.com\/index.php\/2017\/06\/23\/how-to-use-the-microblaze-micro-controller-system-from-labview\/","title":{"rendered":"How to Use the Microblaze Micro Controller System from LabVIEW"},"content":{"rendered":"<p>The MicroBlaze Micro Controller Syste (MCS) is a soft-core processor that can be customized and placed inside the fabric of your FPGA.\u00a0 The uses of this are limitless.<\/p>\n<p><strong>Requirements:<\/strong><\/p>\n<ul class=\"ili-indent\">\n<li>LabVIEW 2017\n<ul>\n<li><a href=\"http:\/\/www.ni.com\/download\/labview-development-system-2017\/6679\/en\/\">http:\/\/www.ni.com\/download\/labview-development-system-2017\/6679\/en\/<\/a><\/li>\n<\/ul>\n<\/li>\n<li>LabVIEW 2017 FPGA Module\n<ul>\n<li><a href=\"http:\/\/www.ni.com\/download\/labview-fpga-module-2017\/6635\/en\/\">http:\/\/www.ni.com\/download\/labview-fpga-module-2017\/6635\/en\/<\/a><\/li>\n<\/ul>\n<\/li>\n<li>LabVIEW 2017 FPGA Module Xilinx Compilation Tools for Vivado 2015.4\n<ul>\n<li><a href=\"http:\/\/www.ni.com\/download\/labview-fpga-module-2017\/6634\/en\/\">http:\/\/www.ni.com\/download\/labview-fpga-module-2017\/6634\/en\/<\/a><\/li>\n<\/ul>\n<\/li>\n<li>Xilinx Software Development Kit version 2015.4\n<ul>\n<li><a href=\"https:\/\/www.xilinx.com\/products\/design-tools\/embedded-software\/sdk.html\">https:\/\/www.xilinx.com\/products\/design-tools\/embedded-software\/sdk.html<\/a><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p><strong>Source Code<\/strong><\/p>\n<p>Browse the source code online via github by visiting the following link:<\/p>\n<ul class=\"ili-indent\">\n<li><a href=\"https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/tree\/master\/05_MicroBlaze_Mcs\/01_MicroBlaze_Mcs_GPIO\">https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/tree\/master\/05_MicroBlaze_Mcs\/01_MicroBlaze_Mcs_GPIO<\/a><\/li>\n<\/ul>\n<p>To download the source code, clone the entire repository with:<\/p>\n<ul class=\"ili-indent\">\n<li>git clone git@github.com:JohnStratoudakis\/LabVIEW_Fpga.git<\/li>\n<\/ul>\n<p>You can also download a zip file with the entire repository:<\/p>\n<ul class=\"ili-indent\">\n<li><a href=\"https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/archive\/master.zip\">https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/archive\/master.zip<\/a><\/li>\n<\/ul>\n<p><strong>What this Guide Accomplishes<\/strong><\/p>\n<p>This guide shows how to use the version of Xilinx Vivado that is bundled with the &#8220;LabVIEW 2017 FPGA Module Xilinx Compilation Tools&#8221; to create a Vivado FPGA design that uses a MicroBlaze MCS core, to create and overlay an executable on top of that core using Xilinx SDK 2015.4, and finally how to import this design and to run it on the National Instruments PXIe-6592R High-Speed Serial Instrument.<\/p>\n<p><strong>References for Further Reading<\/strong><\/p>\n<ul class=\"ili-indent\">\n<li>LabVIEW\n<ul>\n<li><a href=\"http:\/\/www.ni.com\/en-us\/shop\/labview.html\">http:\/\/www.ni.com\/en-us\/shop\/labview.html<\/a><\/li>\n<\/ul>\n<\/li>\n<li>LabVIEW FPGA Module\n<ul>\n<li><a href=\"http:\/\/www.ni.com\/fpga\/\">http:\/\/www.ni.com\/fpga\/<\/a><\/li>\n<\/ul>\n<\/li>\n<li>National Instruments PXIe-6592R (High-Speed Serial Instrument)\n<ul>\n<li><a href=\"http:\/\/www.ni.com\/en-us\/support\/model.pxie-6592.html\">http:\/\/www.ni.com\/en-us\/support\/model.pxie-6592.html<\/a><\/li>\n<\/ul>\n<\/li>\n<li>Xilinx MicroBlaze Micro Controller System\n<ul>\n<li><a href=\"https:\/\/www.xilinx.com\/products\/design-tools\/mb-mcs.html\">https:\/\/www.xilinx.com\/products\/design-tools\/mb-mcs.html<\/a><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p><strong>Slide Share version<\/strong><\/p>\n<p>SlideShare (Opens in new tab)<\/p>\n<p><strong>Video Demonstration of Run<\/strong><\/p>\n<p><iframe loading=\"lazy\" src=\"https:\/\/www.youtube.com\/embed\/FO_zSjt1dFA\" width=\"560\" height=\"315\" frameborder=\"0\" allowfullscreen=\"allowfullscreen\"><\/iframe><\/p>\n<p><em><strong>This guide is broken down in to the following sections:<\/strong><\/em><\/p>\n<ul class=\"ili-indent\">\n<li>Section 1 &#8211; Vivado &#8211; Create MicroBlaze MCS design<\/li>\n<li>Section 2 &#8211; Xilinx SDK &#8211; Write a C Program for the MicroBlaze MCS<\/li>\n<li>Section 3 &#8211; Vivado &#8211; Add Binary (ELF) to MicroBlaze MCS design<\/li>\n<li>Section 4 &#8211; LabVIEW 2017 &#8211; Import design to LabVIEW and run on FPGA<\/li>\n<\/ul>\n<h2><em><strong>Section 1 &#8211; Vivado &#8211; Create MicroBlaze MCS Design<\/strong><\/em><\/h2>\n<p><em><strong>Step 1 &#8211; Start Vivado 2015.4<\/strong><\/em><\/p>\n<p>If you haven&#8217;t set up a shortcut, just run the following batch file:<\/p>\n<ul class=\"ili-indent\">\n<li>C:\\NIFPGA\\programs\\Vivado2015_4\\bin\\vivado.bat<\/li>\n<\/ul>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_01_Start_Vivado_2015.4.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-156 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_01_Start_Vivado_2015.4.png\" alt=\"\" width=\"853\" height=\"693\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_01_Start_Vivado_2015.4.png 853w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_01_Start_Vivado_2015.4-300x244.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_01_Start_Vivado_2015.4-768x624.png 768w\" sizes=\"auto, (max-width: 853px) 100vw, 853px\" \/><\/a><\/p>\n<p><strong>Step 2 &#8211; Create a New Project<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_02_CreateProject.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-157 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_02_CreateProject.png\" alt=\"\" width=\"743\" height=\"528\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_02_CreateProject.png 743w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_02_CreateProject-300x213.png 300w\" sizes=\"auto, (max-width: 743px) 100vw, 743px\" \/><\/a><\/p>\n<p><strong>Step 3 &#8211; Select Project Location and Project Name<\/strong><\/p>\n<p>I created my project in the following location: (screenshot is out of date)<\/p>\n<ul class=\"ili-indent\">\n<li>G:\/work\/git\/LabVIEW_Fpga\/05_MicroBlaze_Mcs\/01_MicroBlaze_MCS_GPIO<\/li>\n<\/ul>\n<p>I named my project &#8220;MicroBlaze_Mcs_GPIO&#8221;<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_03_Set_Project_Location.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-158 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_03_Set_Project_Location.png\" alt=\"\" width=\"743\" height=\"528\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_03_Set_Project_Location.png 743w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_03_Set_Project_Location-300x213.png 300w\" sizes=\"auto, (max-width: 743px) 100vw, 743px\" \/><\/a><\/p>\n<p><strong>Step 4 &#8211; Just click next, I did not set anything here<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_04_Vivado_Select_RTL.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-159 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_04_Vivado_Select_RTL.png\" alt=\"\" width=\"743\" height=\"528\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_04_Vivado_Select_RTL.png 743w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_04_Vivado_Select_RTL-300x213.png 300w\" sizes=\"auto, (max-width: 743px) 100vw, 743px\" \/><\/a><\/p>\n<p><strong>Step 5 &#8211; Make sure the &#8220;Target language&#8221; is VHDL.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_05_Set_Target_Language_VHDL.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-160 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_05_Set_Target_Language_VHDL.png\" alt=\"\" width=\"743\" height=\"528\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_05_Set_Target_Language_VHDL.png 743w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_05_Set_Target_Language_VHDL-300x213.png 300w\" sizes=\"auto, (max-width: 743px) 100vw, 743px\" \/><\/a><\/p>\n<p><strong>Step 6 &#8211; Just click next in the Add Existing IP page<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_06_Add_Existing_IP.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-161 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_06_Add_Existing_IP.png\" alt=\"\" width=\"743\" height=\"528\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_06_Add_Existing_IP.png 743w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_06_Add_Existing_IP-300x213.png 300w\" sizes=\"auto, (max-width: 743px) 100vw, 743px\" \/><\/a><\/p>\n<p><strong>Step 7 &#8211; Click next, we are not adding any constraints, nor do we have to in this project.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_07_Add_Contraints.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-162 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_07_Add_Contraints.png\" alt=\"\" width=\"743\" height=\"528\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_07_Add_Contraints.png 743w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_07_Add_Contraints-300x213.png 300w\" sizes=\"auto, (max-width: 743px) 100vw, 743px\" \/><\/a><\/p>\n<p><strong>Step 8 &#8211; Select the appropriate FPGA part<\/strong><\/p>\n<p>We are using the PXIe-6592R board for this example and the FPGA has the following specifications:<\/p>\n<ul class=\"ili-indent\">\n<li>Family: Kintex-7<\/li>\n<li>Speed Grade: -2<\/li>\n<li>Package: ffg900<\/li>\n<li>Part #: xc7k410t<\/li>\n<\/ul>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_08_Select_Part.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-163 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_08_Select_Part.png\" alt=\"\" width=\"743\" height=\"528\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_08_Select_Part.png 743w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_08_Select_Part-300x213.png 300w\" sizes=\"auto, (max-width: 743px) 100vw, 743px\" \/><\/a><\/p>\n<p><strong>Step 9 &#8211; Click finish to create your new project<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_09_Project_Summary.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-164 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_09_Project_Summary.png\" alt=\"\" width=\"743\" height=\"528\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_09_Project_Summary.png 743w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_09_Project_Summary-300x213.png 300w\" sizes=\"auto, (max-width: 743px) 100vw, 743px\" \/><\/a><\/p>\n<p><strong>Step 10 &#8211; Here is what the project looks like after creation. \u00a0Click on the image below for a higher resolution image to appear in a new window.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_10_Empty_Project.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-165 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_10_Empty_Project.png\" alt=\"\" width=\"1409\" height=\"933\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_10_Empty_Project.png 1409w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_10_Empty_Project-300x199.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_10_Empty_Project-768x509.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_10_Empty_Project-1024x678.png 1024w\" sizes=\"auto, (max-width: 1409px) 100vw, 1409px\" \/><\/a><\/p>\n<p><strong>Step 11 &#8211; Click &#8220;Create Block Design&#8221;<\/strong><\/p>\n<p>Vivado makes it easy to create designs. \u00a0By clicking on create block design, you can make a design that uses several cores and makes it easy to synthesize, package and to export to an application such as LabVIEW<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_11_Create_Block_Design.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-166 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_11_Create_Block_Design.png\" alt=\"\" width=\"204\" height=\"402\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_11_Create_Block_Design.png 204w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_11_Create_Block_Design-152x300.png 152w\" sizes=\"auto, (max-width: 204px) 100vw, 204px\" \/><\/a><\/p>\n<p><strong>Step 12 &#8211; Name the design<\/strong><\/p>\n<p>I like using the d_ prefix followed by a short description of my design. \u00a0Since we are using the MicroBlaze MCS, I name my design &#8220;d_mcs&#8221;<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_12_Set_Block_Design_Name.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-167 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_12_Set_Block_Design_Name.png\" alt=\"\" width=\"426\" height=\"248\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_12_Set_Block_Design_Name.png 426w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_12_Set_Block_Design_Name-300x175.png 300w\" sizes=\"auto, (max-width: 426px) 100vw, 426px\" \/><\/a><\/p>\n<p><strong>Step 13 &#8211; Here is the blank design<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_13_Empty_Block_Design.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-134 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_13_Empty_Block_Design.png\" alt=\"\" width=\"1409\" height=\"933\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_13_Empty_Block_Design.png 1409w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_13_Empty_Block_Design-300x199.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_13_Empty_Block_Design-768x509.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_13_Empty_Block_Design-1024x678.png 1024w\" sizes=\"auto, (max-width: 1409px) 100vw, 1409px\" \/><\/a><\/p>\n<p><strong>Step 14 &#8211; Click the &#8220;Add IP&#8221; button to get a list of all Xilinx available cores<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_14_Add_IP.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-135 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_14_Add_IP.png\" alt=\"\" width=\"294\" height=\"134\" \/><\/a><\/p>\n<p><strong>Step 15 &#8211; Make sure you select the &#8220;MicroBlaze MCS&#8221; and not the &#8220;MicroBlaze&#8221;<\/strong><\/p>\n<p>The MicroBlaze core is more customizable and supports more features, I will cover this in a future article.<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_15_Select_MicroBlaze_MCS.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-136 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_15_Select_MicroBlaze_MCS.png\" alt=\"\" width=\"461\" height=\"380\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_15_Select_MicroBlaze_MCS.png 461w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_15_Select_MicroBlaze_MCS-300x247.png 300w\" sizes=\"auto, (max-width: 461px) 100vw, 461px\" \/><\/a><\/p>\n<p><strong>Step 16 &#8211; After adding the MicroBlaze MCS core. \u00a0Notice that no peripherals have been added, nor has the core been configured.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_16_Block_Design_with_MicroBlaze_MCS.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-137 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_16_Block_Design_with_MicroBlaze_MCS.png\" alt=\"\" width=\"785\" height=\"540\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_16_Block_Design_with_MicroBlaze_MCS.png 785w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_16_Block_Design_with_MicroBlaze_MCS-300x206.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_16_Block_Design_with_MicroBlaze_MCS-768x528.png 768w\" sizes=\"auto, (max-width: 785px) 100vw, 785px\" \/><\/a><\/p>\n<p><strong>Step 17 &#8211; Right click (away from any terminals) and customize the block.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_17_Customize_Block.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-138 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_17_Customize_Block.png\" alt=\"\" width=\"361\" height=\"343\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_17_Customize_Block.png 361w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_17_Customize_Block-300x285.png 300w\" sizes=\"auto, (max-width: 361px) 100vw, 361px\" \/><\/a><\/p>\n<p><strong>Step 18 &#8211; Configure the MicroBlaze MCS core<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_18_Customize_MicroBlaze_MCS_No_Options.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-139 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_18_Customize_MicroBlaze_MCS_No_Options.png\" alt=\"\" width=\"1178\" height=\"814\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_18_Customize_MicroBlaze_MCS_No_Options.png 1178w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_18_Customize_MicroBlaze_MCS_No_Options-300x207.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_18_Customize_MicroBlaze_MCS_No_Options-768x531.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_18_Customize_MicroBlaze_MCS_No_Options-1024x708.png 1024w\" sizes=\"auto, (max-width: 1178px) 100vw, 1178px\" \/><\/a><\/p>\n<p><strong>Step 19 &#8211; Set the memory size to 64 KB and enable the IO Bus if you like. \u00a0I will use the IO Bus in a future article<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_19_Customize_MicroBlaze_MCS_Step_1.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-140 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_19_Customize_MicroBlaze_MCS_Step_1.png\" alt=\"\" width=\"371\" height=\"265\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_19_Customize_MicroBlaze_MCS_Step_1.png 371w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_19_Customize_MicroBlaze_MCS_Step_1-300x214.png 300w\" sizes=\"auto, (max-width: 371px) 100vw, 371px\" \/><\/a><\/p>\n<p><strong>Step 20 &#8211; Enable the General Purpose Output (GPO) channel 1, 32 bits is fine.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_20_Customize_MicroBlaze_MCS_Step_2.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-141 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_20_Customize_MicroBlaze_MCS_Step_2.png\" alt=\"\" width=\"364\" height=\"216\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_20_Customize_MicroBlaze_MCS_Step_2.png 364w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_20_Customize_MicroBlaze_MCS_Step_2-300x178.png 300w\" sizes=\"auto, (max-width: 364px) 100vw, 364px\" \/><\/a><\/p>\n<p><strong>Step 21 &#8211;\u00a0Enable the General Purpose Input (GPI) channel 1, 32 bits is fine.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_21_Customize_MicroBlaze_MCS_Step_3.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-142 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_21_Customize_MicroBlaze_MCS_Step_3.png\" alt=\"\" width=\"333\" height=\"190\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_21_Customize_MicroBlaze_MCS_Step_3.png 333w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_21_Customize_MicroBlaze_MCS_Step_3-300x171.png 300w\" sizes=\"auto, (max-width: 333px) 100vw, 333px\" \/><\/a><\/p>\n<p><strong>Step 22 &#8211; Click on &#8220;Run Connection Automation&#8221; at the top of the window containing the design. Check the Clk box.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_22_Connection_Automation_Step_1.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-143 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_22_Connection_Automation_Step_1.png\" alt=\"\" width=\"758\" height=\"419\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_22_Connection_Automation_Step_1.png 758w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_22_Connection_Automation_Step_1-300x166.png 300w\" sizes=\"auto, (max-width: 758px) 100vw, 758px\" \/><\/a><\/p>\n<p><strong>Step 23 &#8211; The defaults for GPIO2 should be fine as well.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_23_Connection_Automation_Step_2.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-144 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_23_Connection_Automation_Step_2.png\" alt=\"\" width=\"758\" height=\"419\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_23_Connection_Automation_Step_2.png 758w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_23_Connection_Automation_Step_2-300x166.png 300w\" sizes=\"auto, (max-width: 758px) 100vw, 758px\" \/><\/a><\/p>\n<p><strong>Step 24 &#8211; Same for Reset. \u00a0Note how the Reset Polarity is set to ACTIVE_HIGH. \u00a0This will not matter for our design, but it will in other cases. \u00a0i.e. I was dealing with the Arty Artix-7 board, and I had to flip the reset polarity for that board to work.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_24_Connection_Automation_Step_3.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-145 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_24_Connection_Automation_Step_3.png\" alt=\"\" width=\"759\" height=\"424\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_24_Connection_Automation_Step_3.png 759w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_24_Connection_Automation_Step_3-300x168.png 300w\" sizes=\"auto, (max-width: 759px) 100vw, 759px\" \/><\/a><\/p>\n<p><strong>Step 25 &#8211; Now if you enabled the IO Bus, you have to manually make it external. \u00a0Make sure you right-click and that the cursor becomes pencil-like as shown below.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_25_Make_GPIO_External_Step_1.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-146 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_25_Make_GPIO_External_Step_1.png\" alt=\"\" width=\"445\" height=\"256\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_25_Make_GPIO_External_Step_1.png 445w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_25_Make_GPIO_External_Step_1-300x173.png 300w\" sizes=\"auto, (max-width: 445px) 100vw, 445px\" \/><\/a><\/p>\n<p><strong>Step 26 &#8211; Click &#8220;Make External&#8221;<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_26_Make_GPIO_External_Step_2.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-147 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_26_Make_GPIO_External_Step_2.png\" alt=\"\" width=\"543\" height=\"271\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_26_Make_GPIO_External_Step_2.png 543w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_26_Make_GPIO_External_Step_2-300x150.png 300w\" sizes=\"auto, (max-width: 543px) 100vw, 543px\" \/><\/a><\/p>\n<p><strong>Step 27 &#8211; Here is what it looks like after clicking &#8220;Make External&#8221;<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_27_After_Making_GPIO_External.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-148 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_27_After_Making_GPIO_External.png\" alt=\"\" width=\"460\" height=\"229\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_27_After_Making_GPIO_External.png 460w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_27_After_Making_GPIO_External-300x149.png 300w\" sizes=\"auto, (max-width: 460px) 100vw, 460px\" \/><\/a><\/p>\n<p><strong>Step 28 &#8211; Now go back to the block design and right-click on the design containing the MicroBlaze MCS and select &#8220;Generate Output Products&#8221;<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_28_Generate_Output_Products_Step_1.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-149 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_28_Generate_Output_Products_Step_1.png\" alt=\"\" width=\"447\" height=\"323\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_28_Generate_Output_Products_Step_1.png 447w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_28_Generate_Output_Products_Step_1-300x217.png 300w\" sizes=\"auto, (max-width: 447px) 100vw, 447px\" \/><\/a><\/p>\n<p><strong>Step 29 &#8211; Global should be fine.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_29_Generate_Output_Products_Step_2.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-150 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_29_Generate_Output_Products_Step_2.png\" alt=\"\" width=\"313\" height=\"492\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_29_Generate_Output_Products_Step_2.png 313w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_29_Generate_Output_Products_Step_2-191x300.png 191w\" sizes=\"auto, (max-width: 313px) 100vw, 313px\" \/><\/a><\/p>\n<p><strong>Step 30 &#8211; When Vivado is finished, you should see the following.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_30_Generate_Output_Products_Step_3.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-151 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_30_Generate_Output_Products_Step_3.png\" alt=\"\" width=\"370\" height=\"143\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_30_Generate_Output_Products_Step_3.png 370w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_30_Generate_Output_Products_Step_3-300x116.png 300w\" sizes=\"auto, (max-width: 370px) 100vw, 370px\" \/><\/a><\/p>\n<p><strong>Step 31 &#8211; Now right-click on the design and select &#8220;Create HDL Wrapper&#8221;<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_31_Vivado_Create_HDL_Wrapper_Step_1.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-152 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_31_Vivado_Create_HDL_Wrapper_Step_1.png\" alt=\"\" width=\"477\" height=\"330\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_31_Vivado_Create_HDL_Wrapper_Step_1.png 477w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_31_Vivado_Create_HDL_Wrapper_Step_1-300x208.png 300w\" sizes=\"auto, (max-width: 477px) 100vw, 477px\" \/><\/a><\/p>\n<p><strong>Step 32 &#8211; Either option should be fine here, but I like having Vivado manage this for me automatically in case I make changes to my block design.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_32_Vivado_Create_HDL_Wrapper_Step_2.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-153 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_32_Vivado_Create_HDL_Wrapper_Step_2.png\" alt=\"\" width=\"526\" height=\"238\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_32_Vivado_Create_HDL_Wrapper_Step_2.png 526w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_32_Vivado_Create_HDL_Wrapper_Step_2-300x136.png 300w\" sizes=\"auto, (max-width: 526px) 100vw, 526px\" \/><\/a><\/p>\n<p><strong>Step 33 &#8211; Notice how there is a new VHDL file, that contains an instantiation of everything in our Block Design.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_33_Vivado_Create_HDL_Wrapper_Step_3.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-154 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_33_Vivado_Create_HDL_Wrapper_Step_3.png\" alt=\"\" width=\"440\" height=\"200\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_33_Vivado_Create_HDL_Wrapper_Step_3.png 440w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_33_Vivado_Create_HDL_Wrapper_Step_3-300x136.png 300w\" sizes=\"auto, (max-width: 440px) 100vw, 440px\" \/><\/a><\/p>\n<p><strong>Step 34 &#8211; A preview of the contents of the VHDL design wrapper. \u00a0From LabVIEW we will be importing this wrapper.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_34_Vivado_Create_HDL_Wrapper_Step_4.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-155 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_34_Vivado_Create_HDL_Wrapper_Step_4.png\" alt=\"\" width=\"744\" height=\"329\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_34_Vivado_Create_HDL_Wrapper_Step_4.png 744w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_34_Vivado_Create_HDL_Wrapper_Step_4-300x133.png 300w\" sizes=\"auto, (max-width: 744px) 100vw, 744px\" \/><\/a><\/p>\n<h2><em><strong>Section 2 &#8211; Xilinx SDK Write a C program<\/strong><\/em><\/h2>\n<p><strong>Step 1 &#8211; Now we take a break from Vivado and launch the Xilinx SDK. \u00a0You can normally export the hardware from Vivado and ask it to launch the SDK, but there is a bug in this version of Vivado (2015.4) that prevents us from doing so only in the case that our design is using the MicroBlaze MCS. \u00a0Note that this does not apply to designs using the MicroBlaze core.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_01_Splash.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-183 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_01_Splash.png\" alt=\"\" width=\"550\" height=\"330\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_01_Splash.png 550w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_01_Splash-300x180.png 300w\" sizes=\"auto, (max-width: 550px) 100vw, 550px\" \/><\/a><\/p>\n<p><strong>Step 2 &#8211; Create a directory named &#8220;MicroBlaze_Mcs_GPIO.sdk&#8221; as a sub-directory inside the Vivado project directory and set this to be your workspace.<\/strong><\/p>\n<p>Normally, if you select &#8220;File-&gt;Export-&gt;Hardware&#8221;, this directory will automatically be created for you, but remember that the hdf file that will exist in the root directory will not work due to a bug in Vivado 2015.4, so I typically create the directory myself.<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_02_Set_Workspace.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-184 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_02_Set_Workspace.png\" alt=\"\" width=\"620\" height=\"281\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_02_Set_Workspace.png 620w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_02_Set_Workspace-300x136.png 300w\" sizes=\"auto, (max-width: 620px) 100vw, 620px\" \/><\/a><\/p>\n<p><strong>Step 3 &#8211; Click &#8220;File-&gt;New-&gt;Other&#8221; to get to the New Project Wizard.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_03_New_Project_Other.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-170 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_03_New_Project_Other.png\" alt=\"\" width=\"598\" height=\"376\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_03_New_Project_Other.png 598w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_03_New_Project_Other-300x189.png 300w\" sizes=\"auto, (max-width: 598px) 100vw, 598px\" \/><\/a><\/p>\n<p><strong>Step 4 &#8211; Select Hardware Specification.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_04_Hardware_Platform_Specification.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-171 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_04_Hardware_Platform_Specification.png\" alt=\"\" width=\"525\" height=\"500\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_04_Hardware_Platform_Specification.png 525w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_04_Hardware_Platform_Specification-300x286.png 300w\" sizes=\"auto, (max-width: 525px) 100vw, 525px\" \/><\/a><\/p>\n<p><strong>Step 5 &#8211; Click the &#8220;Browse&#8221; button and add the following file, make sure you select the file ending with &#8220;_sdk.xml&#8221;<\/strong><\/p>\n<p>The full path from the root of the Vivado project is as follows:<\/p>\n<p>MicroBlaze_Mcs_GPIO.srcs\\sources_1\\bd\\d_mcs\\ip\\d_mcs_microblaze_mcs_0_0\\d_mcs_microblaze_mcs_0_0_sdk.xml<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_05_Hardware_Platform_Specification_Pick_Sdk_Xml.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-172 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_05_Hardware_Platform_Specification_Pick_Sdk_Xml.png\" alt=\"\" width=\"960\" height=\"540\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_05_Hardware_Platform_Specification_Pick_Sdk_Xml.png 960w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_05_Hardware_Platform_Specification_Pick_Sdk_Xml-300x169.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_05_Hardware_Platform_Specification_Pick_Sdk_Xml-768x432.png 768w\" sizes=\"auto, (max-width: 960px) 100vw, 960px\" \/><\/a><\/p>\n<p><strong>Step 6 &#8211; The default name is okay, just click Finish after selecting the XML file from the step above.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_06_Hardware_Platform_Specification_Finished.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-173 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_06_Hardware_Platform_Specification_Finished.png\" alt=\"\" width=\"1240\" height=\"502\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_06_Hardware_Platform_Specification_Finished.png 1240w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_06_Hardware_Platform_Specification_Finished-300x121.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_06_Hardware_Platform_Specification_Finished-768x311.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_06_Hardware_Platform_Specification_Finished-1024x415.png 1024w\" sizes=\"auto, (max-width: 1240px) 100vw, 1240px\" \/><\/a><\/p>\n<p><strong>Step 7 &#8211; What the new project looks like. \u00a0Notice the Target FPGA Device and the address map.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_07_After.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-174 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_07_After.png\" alt=\"\" width=\"1024\" height=\"832\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_07_After.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_07_After-300x244.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_07_After-768x624.png 768w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/a><\/p>\n<p><strong>Step 8 &#8211; Now create a new Application Project.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_08_New_Application_Project.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-175 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_08_New_Application_Project.png\" alt=\"\" width=\"645\" height=\"175\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_08_New_Application_Project.png 645w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_08_New_Application_Project-300x81.png 300w\" sizes=\"auto, (max-width: 645px) 100vw, 645px\" \/><\/a><\/p>\n<p><strong>Step 9 &#8211; Call this project &#8220;gpio_rw&#8221;, our project will read from GPI-1 and write out of GPO-1.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_09_New_Application_Project_Set_Name.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-176 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_09_New_Application_Project_Set_Name.png\" alt=\"\" width=\"525\" height=\"665\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_09_New_Application_Project_Set_Name.png 525w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_09_New_Application_Project_Set_Name-237x300.png 237w\" sizes=\"auto, (max-width: 525px) 100vw, 525px\" \/><\/a><\/p>\n<p><strong>Step 10 &#8211; Select Empty Application, I will provide the code that you should insert.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_10_New_Application_Project_Set_Type.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-177 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_10_New_Application_Project_Set_Type.png\" alt=\"\" width=\"525\" height=\"665\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_10_New_Application_Project_Set_Type.png 525w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_10_New_Application_Project_Set_Type-237x300.png 237w\" sizes=\"auto, (max-width: 525px) 100vw, 525px\" \/><\/a><\/p>\n<p><strong>Step 11 &#8211; Right click on the &#8220;src&#8221; directory to create a new C source.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_11_After_New_Project.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-178 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_11_After_New_Project.png\" alt=\"\" width=\"332\" height=\"351\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_11_After_New_Project.png 332w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_11_After_New_Project-284x300.png 284w\" sizes=\"auto, (max-width: 332px) 100vw, 332px\" \/><\/a><\/p>\n<p><strong>Step 12 &#8211; After right-clicking, select &#8220;New-&gt;Source File&#8221;<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_12_New_Source.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-179 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_12_New_Source.png\" alt=\"\" width=\"553\" height=\"291\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_12_New_Source.png 553w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_12_New_Source-300x158.png 300w\" sizes=\"auto, (max-width: 553px) 100vw, 553px\" \/><\/a><\/p>\n<p><strong>Step 13 &#8211; Name this file main.c<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_13_New_Source_C.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-180 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_13_New_Source_C.png\" alt=\"\" width=\"537\" height=\"433\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_13_New_Source_C.png 537w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_13_New_Source_C-300x242.png 300w\" sizes=\"auto, (max-width: 537px) 100vw, 537px\" \/><\/a><\/p>\n<p><strong>Step 14 &#8211; Copy and Paste the following source code:<\/strong><\/p>\n<p><a href=\"https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/blob\/master\/05_MicroBlaze_Mcs\/01_MicroBlaze_Mcs_GPIO\/MicroBlaze_Mcs_GPIO\/MicroBlaze_Mcs_GPIO.sdk\/gpio_rw\/src\/main.c\">https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/blob\/master\/05_MicroBlaze_Mcs\/01_MicroBlaze_Mcs_GPIO\/MicroBlaze_Mcs_GPIO\/MicroBlaze_Mcs_GPIO.sdk\/gpio_rw\/src\/main.c<\/a><\/p>\n<table style=\"height: 113px;\" width=\"579\">\n<tbody>\n<tr>\n<td style=\"width: 578px;\">\/*<br \/>\n* main.c<br \/>\n*<br \/>\n* Created on: Jun 17, 2017<br \/>\n* Author: John<br \/>\n*\/#include &#8220;xparameters.h&#8221;<br \/>\n#include &#8220;xil_cache.h&#8221;<br \/>\n#include &#8220;xiomodule.h&#8221;int main()<br \/>\n{Xil_ICacheEnable();Xil_DCacheEnable();print(&#8220;&#8212;Entering main&#8212;\\n\\r&#8221;);{<\/p>\n<p>XIOModule gpioIn_1;<\/p>\n<p>XIOModule_Initialize(&amp;gpioIn_1, XPAR_IOMODULE_0_DEVICE_ID);<\/p>\n<p>XIOModule_Start(&amp;gpioIn_1);<\/p>\n<p>XIOModule gpioOut_1;<\/p>\n<p>XIOModule_Initialize(&amp;gpioOut_1, XPAR_IOMODULE_0_DEVICE_ID);<\/p>\n<p>XIOModule_Start(&amp;gpioOut_1);<\/p>\n<p>u32 gpi_1;<\/p>\n<p>while(1)<\/p>\n<p>{<\/p>\n<p>gpi_1 = XIOModule_DiscreteRead(&amp;gpioIn_1, 1);<\/p>\n<p>if(gpi_1 == 0)<\/p>\n<p>{<\/p>\n<p>gpi_1 = 50;<\/p>\n<p>}<\/p>\n<p>XIOModule_DiscreteWrite(&amp;gpioOut_1, 1, gpi_1 + gpi_1);<\/p>\n<p>}<\/p>\n<p>}<\/p>\n<p>print(&#8220;&#8212;Exiting main&#8212;\\n\\r&#8221;);<\/p>\n<p>Xil_DCacheDisable();<\/p>\n<p>Xil_ICacheDisable();<\/p>\n<p>return 0;<\/p>\n<p>}<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_14_Create_Main.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-181 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_14_Create_Main.png\" alt=\"\" width=\"504\" height=\"514\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_14_Create_Main.png 504w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_14_Create_Main-294x300.png 294w\" sizes=\"auto, (max-width: 504px) 100vw, 504px\" \/><\/a><\/p>\n<p><strong>Step 15 &#8211; Building should automatically take place when you save the source file. \u00a0But click &#8220;Project-&gt;Build All&#8221; to confirm this.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_15_Build_All.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-182 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_SDK_15_Build_All.png\" alt=\"\" width=\"297\" height=\"194\" \/><\/a><\/p>\n<h2><em><strong>Section 3 &#8211; Vivado Part 2<\/strong><\/em><\/h2>\n<p><strong>Step 1 &#8211; Go back to your Vivado project and select &#8220;Tools-&gt;Associate ELF Files&#8230;&#8221;<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_01_Vivado_Associate_Elf_Step_1.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-193 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_01_Vivado_Associate_Elf_Step_1.png\" alt=\"\" width=\"380\" height=\"205\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_01_Vivado_Associate_Elf_Step_1.png 380w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_01_Vivado_Associate_Elf_Step_1-300x162.png 300w\" sizes=\"auto, (max-width: 380px) 100vw, 380px\" \/><\/a><\/p>\n<p><strong>Step 2 &#8211; Click the &#8220;&#8230;&#8221; button next to the elf file, which should be &#8220;mb_bootloop_le.elf&#8221; for both Design Sources and Simulation Sources.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_02_Vivado_Associate_Elf_Step_2.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-186 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_02_Vivado_Associate_Elf_Step_2.png\" alt=\"\" width=\"540\" height=\"396\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_02_Vivado_Associate_Elf_Step_2.png 540w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_02_Vivado_Associate_Elf_Step_2-300x220.png 300w\" sizes=\"auto, (max-width: 540px) 100vw, 540px\" \/><\/a><\/p>\n<p><strong>Step 3 &#8211; Add your binary, which should be located in the following directory:<\/strong><\/p>\n<p>MicroBlaze_Mcs_GPIO\/MicroBlaze_Mcs_GPIO.sdk\/gpio_rw\/src\/Debug\/gpio_rw.elf<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_03_Vivado_Associate_Elf_Step_3.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-187 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_03_Vivado_Associate_Elf_Step_3.png\" alt=\"\" width=\"1366\" height=\"638\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_03_Vivado_Associate_Elf_Step_3.png 1366w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_03_Vivado_Associate_Elf_Step_3-300x140.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_03_Vivado_Associate_Elf_Step_3-768x359.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_03_Vivado_Associate_Elf_Step_3-1024x478.png 1024w\" sizes=\"auto, (max-width: 1366px) 100vw, 1366px\" \/><\/a><\/p>\n<p><strong>Step 4 &#8211; Click ok, the new elf file should automatically be selected.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_04_Vivado_Associate_Elf_Step_4.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-188 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_04_Vivado_Associate_Elf_Step_4.png\" alt=\"\" width=\"540\" height=\"346\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_04_Vivado_Associate_Elf_Step_4.png 540w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_04_Vivado_Associate_Elf_Step_4-300x192.png 300w\" sizes=\"auto, (max-width: 540px) 100vw, 540px\" \/><\/a><\/p>\n<p><strong>Step 5 &#8211; Now run the Synthesis.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_05_Run_Synthesis.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-189 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_05_Run_Synthesis.png\" alt=\"\" width=\"198\" height=\"290\" \/><\/a><\/p>\n<p><strong>Step 6 &#8211; You can verify that synthesis is running by looking at the top-right of the Vivado Window.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_06_Synthesis_Running.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-190 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_06_Synthesis_Running.png\" alt=\"\" width=\"322\" height=\"139\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_06_Synthesis_Running.png 322w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_06_Synthesis_Running-300x130.png 300w\" sizes=\"auto, (max-width: 322px) 100vw, 322px\" \/><\/a><\/p>\n<p><strong>Step 7 &#8211; After a couple of minutes when Synthesis finishes, click Cancel, because we do not want to run the implementation. \u00a0LabVIEW will handle that!<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_07_Synthesis_Finished_hit_Cancel.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-191 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_07_Synthesis_Finished_hit_Cancel.png\" alt=\"\" width=\"355\" height=\"296\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_07_Synthesis_Finished_hit_Cancel.png 355w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_07_Synthesis_Finished_hit_Cancel-300x250.png 300w\" sizes=\"auto, (max-width: 355px) 100vw, 355px\" \/><\/a><\/p>\n<p><strong>Step 8 &#8211; Write a checkpoint by clicking &#8220;File-&gt;Write Checkpoint&#8221;<\/strong><\/p>\n<p>Note that you must write a Synthesized Checkpoint, which means that you have to have followed the steps above and not have run Implementation. \u00a0If you run implementation, the checkpoint file will be larger than if you only ran synthesis. In case you made a mistake and implemented your design, simply open the Synthesized design and write a new checkpoint.<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_08_Vivado_Write_Checkpoint.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-192 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_08_Vivado_Write_Checkpoint.png\" alt=\"\" width=\"550\" height=\"164\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_08_Vivado_Write_Checkpoint.png 550w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_Vivado_Part_2_08_Vivado_Write_Checkpoint-300x89.png 300w\" sizes=\"auto, (max-width: 550px) 100vw, 550px\" \/><\/a><\/p>\n<h2><em><strong>Section 4 &#8211; LabVIEW 2017<\/strong><\/em><\/h2>\n<p><strong>Step 1 &#8211; LabVIEW 2017 splash screen. \u00a0I like the new look.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_01_Splash.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-220 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_01_Splash.png\" alt=\"\" width=\"772\" height=\"473\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_01_Splash.png 772w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_01_Splash-300x184.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_01_Splash-768x471.png 768w\" sizes=\"auto, (max-width: 772px) 100vw, 772px\" \/><\/a><\/p>\n<p><strong>Step 2 &#8211; Create a new Project.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_02_Create_or_OpenProjectt.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-221 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_02_Create_or_OpenProjectt.png\" alt=\"\" width=\"800\" height=\"544\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_02_Create_or_OpenProjectt.png 800w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_02_Create_or_OpenProjectt-300x204.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_02_Create_or_OpenProjectt-768x522.png 768w\" sizes=\"auto, (max-width: 800px) 100vw, 800px\" \/><\/a><\/p>\n<p><strong>Step 3 &#8211; Blank Project is fine.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_03_CreateProject.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-222 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_03_CreateProject.png\" alt=\"\" width=\"816\" height=\"638\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_03_CreateProject.png 816w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_03_CreateProject-300x235.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_03_CreateProject-768x600.png 768w\" sizes=\"auto, (max-width: 816px) 100vw, 816px\" \/><\/a><\/p>\n<p><strong>Step 4 &#8211; Here is what an empty project looks like before you save it.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_04_BlankProject.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-223 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_04_BlankProject.png\" alt=\"\" width=\"392\" height=\"545\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_04_BlankProject.png 392w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_04_BlankProject-216x300.png 216w\" sizes=\"auto, (max-width: 392px) 100vw, 392px\" \/><\/a><\/p>\n<p><strong>Step 5 &#8211; Add a new target, for this tutorial we are going to be using the PXIe-6592R High-Speed Serial Instrument.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_05_AddTarget.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-224 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_05_AddTarget.png\" alt=\"\" width=\"417\" height=\"335\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_05_AddTarget.png 417w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_05_AddTarget-300x241.png 300w\" sizes=\"auto, (max-width: 417px) 100vw, 417px\" \/><\/a><\/p>\n<p><strong>Step 6 &#8211; If you do not have live hardware plugged in, select New target or device, if you do, it should show up automatically.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_06_Select_6592.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-225 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_06_Select_6592.png\" alt=\"\" width=\"459\" height=\"507\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_06_Select_6592.png 459w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_06_Select_6592-272x300.png 272w\" sizes=\"auto, (max-width: 459px) 100vw, 459px\" \/><\/a><\/p>\n<p><strong>Step 7 &#8211; After adding the PXIe-6592R<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_07_Project_w_6592.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-226 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_07_Project_w_6592.png\" alt=\"\" width=\"392\" height=\"545\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_07_Project_w_6592.png 392w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_07_Project_w_6592-216x300.png 216w\" sizes=\"auto, (max-width: 392px) 100vw, 392px\" \/><\/a><\/p>\n<p><strong>Step 8 &#8211; Click File-&gt;Save and save the project.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_08_SaveProject.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-227 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_08_SaveProject.png\" alt=\"\" width=\"720\" height=\"480\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_08_SaveProject.png 720w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_08_SaveProject-300x200.png 300w\" sizes=\"auto, (max-width: 720px) 100vw, 720px\" \/><\/a><\/p>\n<p><strong>Step 9 &#8211; Add a new FPGA-scoped VI. \u00a0Make sure you right-click on the FPGA-target for this.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_09_Create_Fpga_TopLevel.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-228 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_09_Create_Fpga_TopLevel.png\" alt=\"\" width=\"458\" height=\"160\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_09_Create_Fpga_TopLevel.png 458w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_09_Create_Fpga_TopLevel-300x105.png 300w\" sizes=\"auto, (max-width: 458px) 100vw, 458px\" \/><\/a><\/p>\n<p><strong>Step 10 &#8211; I opened the VI and cleaned up the windows and show the block diagram here.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_10_With_TopLevel.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-229 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_10_With_TopLevel.png\" alt=\"\" width=\"1060\" height=\"757\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_10_With_TopLevel.png 1060w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_10_With_TopLevel-300x214.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_10_With_TopLevel-768x548.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_10_With_TopLevel-1024x731.png 1024w\" sizes=\"auto, (max-width: 1060px) 100vw, 1060px\" \/><\/a><\/p>\n<p><strong>Step 11 &#8211; Now click &#8220;File-&gt;Save&#8221; to save the FPGA-scoped VI<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_11_Save_TopLevel.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-230 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_11_Save_TopLevel.png\" alt=\"\" width=\"320\" height=\"235\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_11_Save_TopLevel.png 320w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_11_Save_TopLevel-300x220.png 300w\" sizes=\"auto, (max-width: 320px) 100vw, 320px\" \/><\/a><\/p>\n<p><strong>Step 12 &#8211; I usually save FPGA-scoped VIs in a sub-directory named after the FPGA target. \u00a0In this case &#8220;Fpga-6592&#8221;<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_12_Save_in_SubDir.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-231 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_12_Save_in_SubDir.png\" alt=\"\" width=\"720\" height=\"480\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_12_Save_in_SubDir.png 720w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_12_Save_in_SubDir-300x200.png 300w\" sizes=\"auto, (max-width: 720px) 100vw, 720px\" \/><\/a><\/p>\n<p><strong>Step 13 &#8211; Right-click anywhere in the blank white space and select &#8220;Timed Loop&#8221; to add a Single-Cycle Timed Loop.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_13_Create_SGTL.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-232 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_13_Create_SGTL.png\" alt=\"\" width=\"621\" height=\"328\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_13_Create_SGTL.png 621w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_13_Create_SGTL-300x158.png 300w\" sizes=\"auto, (max-width: 621px) 100vw, 621px\" \/><\/a><\/p>\n<p><strong>Step 14 &#8211; Add a new FPGA clock since the default of 40 MHz is not suitable for our 100 MHz MicroBlaze MCS.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_14_Create_Derived_Clock.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-233 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_14_Create_Derived_Clock.png\" alt=\"\" width=\"371\" height=\"339\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_14_Create_Derived_Clock.png 371w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_14_Create_Derived_Clock-300x274.png 300w\" sizes=\"auto, (max-width: 371px) 100vw, 371px\" \/><\/a><\/p>\n<p><strong>Step 15 &#8211; Just type 100 in the &#8220;Desired Derived Frequency box and click ok<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_15_Create_Derived_Clock_100MHz.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-195 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_15_Create_Derived_Clock_100MHz.png\" alt=\"\" width=\"827\" height=\"584\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_15_Create_Derived_Clock_100MHz.png 827w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_15_Create_Derived_Clock_100MHz-300x212.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_15_Create_Derived_Clock_100MHz-768x542.png 768w\" sizes=\"auto, (max-width: 827px) 100vw, 827px\" \/><\/a><\/p>\n<p><strong>Step 16 &#8211; Now right-click on the clock input to the Single-Cycle Timed Loop and select Create-&gt;Constant<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_16_Create_ClockConstant.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-196 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_16_Create_ClockConstant.png\" alt=\"\" width=\"411\" height=\"280\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_16_Create_ClockConstant.png 411w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_16_Create_ClockConstant-300x204.png 300w\" sizes=\"auto, (max-width: 411px) 100vw, 411px\" \/><\/a><\/p>\n<p><strong>Step 17 &#8211; Here is what the loop looks like before selecting the clock type.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_17_With_ClockConstant.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-197 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_17_With_ClockConstant.png\" alt=\"\" width=\"768\" height=\"498\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_17_With_ClockConstant.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_17_With_ClockConstant-300x195.png 300w\" sizes=\"auto, (max-width: 768px) 100vw, 768px\" \/><\/a><\/p>\n<p><strong>Step 18 &#8211; Dropdown should reveal 2 clocks. \u00a0You select 100 MHz<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_18_SelectClock.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-198 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_18_SelectClock.png\" alt=\"\" width=\"227\" height=\"159\" \/><\/a><\/p>\n<p><strong>Step 19 &#8211; After selecting 100 MHz<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_19_With_100MHz_Clock.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-199 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_19_With_100MHz_Clock.png\" alt=\"\" width=\"221\" height=\"124\" \/><\/a><\/p>\n<p><strong>Step 20 &#8211; Now to configure the CLIP node. \u00a0CLIP stands for Component Level IP.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_80_Create_CLIP.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-200 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_80_Create_CLIP.png\" alt=\"\" width=\"432\" height=\"408\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_80_Create_CLIP.png 432w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_80_Create_CLIP-300x283.png 300w\" sizes=\"auto, (max-width: 432px) 100vw, 432px\" \/><\/a><\/p>\n<p><strong>Step 21 &#8211; Click Component-Level IP in the left, and then click on the Create File icon on the right.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_81_Create_CLIP_Create_File.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-201 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_81_Create_CLIP_Create_File.png\" alt=\"\" width=\"814\" height=\"581\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_81_Create_CLIP_Create_File.png 814w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_81_Create_CLIP_Create_File-300x214.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_81_Create_CLIP_Create_File-768x548.png 768w\" sizes=\"auto, (max-width: 814px) 100vw, 814px\" \/><\/a><\/p>\n<p><strong>Step 22 &#8211; Add the checkpoint dcp file, and the wrapper vhdl file.<\/strong><\/p>\n<p>The wrapper file can be found here:<\/p>\n<p><a href=\"https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/blob\/master\/05_MicroBlaze_Mcs\/01_MicroBlaze_Mcs_GPIO\/d_mcs_wrapper_top.vhd\">https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/blob\/master\/05_MicroBlaze_Mcs\/01_MicroBlaze_Mcs_GPIO\/d_mcs_wrapper_top.vhd<\/a><\/p>\n<p>I also have a sample checkpoint file, but you ideally want to create this yourself:<\/p>\n<p><a href=\"https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/blob\/master\/05_MicroBlaze_Mcs\/01_MicroBlaze_Mcs_GPIO\/MicroBlaze_Mcs_GPIO\/checkpoint_4.dcp\">https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/blob\/master\/05_MicroBlaze_Mcs\/01_MicroBlaze_Mcs_GPIO\/MicroBlaze_Mcs_GPIO\/checkpoint_4.dcp<\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_82_Create_CLIP_Step_1_of_8.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-202 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_82_Create_CLIP_Step_1_of_8.png\" alt=\"\" width=\"838\" height=\"614\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_82_Create_CLIP_Step_1_of_8.png 838w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_82_Create_CLIP_Step_1_of_8-300x220.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_82_Create_CLIP_Step_1_of_8-768x563.png 768w\" sizes=\"auto, (max-width: 838px) 100vw, 838px\" \/><\/a><\/p>\n<p><strong>Step 23 &#8211; Depending on your target, you may have to limit the device families.\u00a0<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_83_Create_CLIP_Step_2_of_8.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-203 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_83_Create_CLIP_Step_2_of_8.png\" alt=\"\" width=\"838\" height=\"614\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_83_Create_CLIP_Step_2_of_8.png 838w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_83_Create_CLIP_Step_2_of_8-300x220.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_83_Create_CLIP_Step_2_of_8-768x563.png 768w\" sizes=\"auto, (max-width: 838px) 100vw, 838px\" \/><\/a><\/p>\n<p><strong>Step 24 &#8211; Click Chek Syntax, this requires the Vivado Compilation Tools to be installed in order to work.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_84_Create_CLIP_Step_3_of_8.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-204 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_84_Create_CLIP_Step_3_of_8.png\" alt=\"\" width=\"838\" height=\"614\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_84_Create_CLIP_Step_3_of_8.png 838w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_84_Create_CLIP_Step_3_of_8-300x220.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_84_Create_CLIP_Step_3_of_8-768x563.png 768w\" sizes=\"auto, (max-width: 838px) 100vw, 838px\" \/><\/a><\/p>\n<p><strong>Step 25 &#8211; Set the reset_rtl Signal type to be reset, the clock_rtl signal type to be clock, and set the data type for the gpio_rtl_tri_i and gpio_rtl_tri_o to be U32.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_85_Create_CLIP_Step_4_of_8.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-205 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_85_Create_CLIP_Step_4_of_8.png\" alt=\"\" width=\"838\" height=\"614\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_85_Create_CLIP_Step_4_of_8.png 838w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_85_Create_CLIP_Step_4_of_8-300x220.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_85_Create_CLIP_Step_4_of_8-768x563.png 768w\" sizes=\"auto, (max-width: 838px) 100vw, 838px\" \/><\/a><\/p>\n<p><strong>Step 26 &#8211; Nothing to do here, just click next.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_86_Create_CLIP_Step_5_of_8.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-206 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_86_Create_CLIP_Step_5_of_8.png\" alt=\"\" width=\"838\" height=\"614\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_86_Create_CLIP_Step_5_of_8.png 838w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_86_Create_CLIP_Step_5_of_8-300x220.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_86_Create_CLIP_Step_5_of_8-768x563.png 768w\" sizes=\"auto, (max-width: 838px) 100vw, 838px\" \/><\/a><\/p>\n<p><strong>Step 27 &#8211; Nothing to do here, just click next.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_87_Create_CLIP_Step_6_of_8.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-207 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_87_Create_CLIP_Step_6_of_8.png\" alt=\"\" width=\"838\" height=\"614\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_87_Create_CLIP_Step_6_of_8.png 838w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_87_Create_CLIP_Step_6_of_8-300x220.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_87_Create_CLIP_Step_6_of_8-768x563.png 768w\" sizes=\"auto, (max-width: 838px) 100vw, 838px\" \/><\/a><\/p>\n<p><strong>Step 28 &#8211; Use the shift key and the mouse to select all signals on the left, and make them all require the clock_rtl clock domain and to be required to be inside a Single-Cycle Timed Loop.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_87_Create_CLIP_Step_7_of_8.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-208 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_87_Create_CLIP_Step_7_of_8.png\" alt=\"\" width=\"838\" height=\"614\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_87_Create_CLIP_Step_7_of_8.png 838w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_87_Create_CLIP_Step_7_of_8-300x220.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_87_Create_CLIP_Step_7_of_8-768x563.png 768w\" sizes=\"auto, (max-width: 838px) 100vw, 838px\" \/><\/a><\/p>\n<p><strong>Step 29 &#8211; Click Finish<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_88_Create_CLIP_Step_8_of_8.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-209 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_88_Create_CLIP_Step_8_of_8.png\" alt=\"\" width=\"838\" height=\"614\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_88_Create_CLIP_Step_8_of_8.png 838w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_88_Create_CLIP_Step_8_of_8-300x220.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_88_Create_CLIP_Step_8_of_8-768x563.png 768w\" sizes=\"auto, (max-width: 838px) 100vw, 838px\" \/><\/a><\/p>\n<p><strong>Step 30 &#8211; And now you have a CLIP available to your project.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_89_After_Create_Clip.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-210 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_89_After_Create_Clip.png\" alt=\"\" width=\"827\" height=\"584\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_89_After_Create_Clip.png 827w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_89_After_Create_Clip-300x212.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_89_After_Create_Clip-768x542.png 768w\" sizes=\"auto, (max-width: 827px) 100vw, 827px\" \/><\/a><\/p>\n<p><strong>Step 31 &#8211; Now create an instance of this CLIP by clicking New-&gt;Component Level IP<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_90_Add_Clip.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-211 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_90_Add_Clip.png\" alt=\"\" width=\"507\" height=\"374\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_90_Add_Clip.png 507w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_90_Add_Clip-300x221.png 300w\" sizes=\"auto, (max-width: 507px) 100vw, 507px\" \/><\/a><\/p>\n<p><strong>Step 32 &#8211; Select the ip from the drop down, I usually name the instance to match what is in the wrapper vhdl file. \u00a0In older versions of LabVIEW this was required, but I am not sure if that is still the case.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_91_Add_CliStep_2.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-212 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_91_Add_CliStep_2.png\" alt=\"\" width=\"827\" height=\"584\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_91_Add_CliStep_2.png 827w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_91_Add_CliStep_2-300x212.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_91_Add_CliStep_2-768x542.png 768w\" sizes=\"auto, (max-width: 827px) 100vw, 827px\" \/><\/a><\/p>\n<p><strong>Step 33 &#8211; Select the appropriate clock<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_92_Add_Clip_Step_3.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-213 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_92_Add_Clip_Step_3.png\" alt=\"\" width=\"827\" height=\"584\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_92_Add_Clip_Step_3.png 827w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_92_Add_Clip_Step_3-300x212.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_92_Add_Clip_Step_3-768x542.png 768w\" sizes=\"auto, (max-width: 827px) 100vw, 827px\" \/><\/a><\/p>\n<p><strong>Step 34 &#8211; What the project looks like with the added CLIP after expanding it.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_93_After_add_Clip.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-214 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_93_After_add_Clip.png\" alt=\"\" width=\"392\" height=\"545\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_93_After_add_Clip.png 392w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_93_After_add_Clip-216x300.png 216w\" sizes=\"auto, (max-width: 392px) 100vw, 392px\" \/><\/a><\/p>\n<p><strong>Step 35 &#8211; Inside the Single-Cycle Timed Loop, right-click and select an &#8220;I\/O Node&#8221;<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_94_Add_IO_Node.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-215 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_94_Add_IO_Node.png\" alt=\"\" width=\"893\" height=\"612\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_94_Add_IO_Node.png 893w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_94_Add_IO_Node-300x206.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_94_Add_IO_Node-768x526.png 768w\" sizes=\"auto, (max-width: 893px) 100vw, 893px\" \/><\/a><\/p>\n<p><strong>Step 36 &#8211; From here select the gpio_rtl_i, and gpio_rtl_o signals.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_95_Add_IO_Node_Step_2.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-216 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_95_Add_IO_Node_Step_2.png\" alt=\"\" width=\"712\" height=\"488\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_95_Add_IO_Node_Step_2.png 712w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_95_Add_IO_Node_Step_2-300x206.png 300w\" sizes=\"auto, (max-width: 712px) 100vw, 712px\" \/><\/a><\/p>\n<p><strong>Step 37 &#8211; Add a control to the input, and an indicator to the output.<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_96_Read_to_Build.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-217 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_96_Read_to_Build.png\" alt=\"\" width=\"1202\" height=\"748\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_96_Read_to_Build.png 1202w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_96_Read_to_Build-300x187.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_96_Read_to_Build-768x478.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_96_Read_to_Build-1024x637.png 1024w\" sizes=\"auto, (max-width: 1202px) 100vw, 1202px\" \/><\/a><\/p>\n<p><strong>Step 38 &#8211; Create a Build Specification<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_97_Create_Build_Specification.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-218 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_97_Create_Build_Specification.png\" alt=\"\" width=\"413\" height=\"675\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_97_Create_Build_Specification.png 413w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_97_Create_Build_Specification-184x300.png 184w\" sizes=\"auto, (max-width: 413px) 100vw, 413px\" \/><\/a><\/p>\n<p><strong>Step 39 &#8211; And build it!\u00a0<\/strong><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_98_Build.png\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-219 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_98_Build.png\" alt=\"\" width=\"356\" height=\"347\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_98_Build.png 356w, https:\/\/fpganow.com\/wp-content\/uploads\/2017\/06\/mcs_1_LV_2017_98_Build-300x292.png 300w\" sizes=\"auto, (max-width: 356px) 100vw, 356px\" \/><\/a><\/p>\n<p>You can now run the top-level VI. \u00a0Video demonstration to come shortly.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>The MicroBlaze Micro Controller Syste (MCS) is a soft-core processor that can be customized and placed inside the fabric of your FPGA.\u00a0 The uses of this are limitless. Requirements: LabVIEW 2017 http:\/\/www.ni.com\/download\/labview-development-system-2017\/6679\/en\/ LabVIEW 2017 FPGA Module http:\/\/www.ni.com\/download\/labview-fpga-module-2017\/6635\/en\/ LabVIEW 2017 FPGA Module Xilinx Compilation Tools for Vivado 2015.4 http:\/\/www.ni.com\/download\/labview-fpga-module-2017\/6634\/en\/ Xilinx Software Development Kit version 2015.4 https:\/\/www.xilinx.com\/products\/design-tools\/embedded-software\/sdk.html &#8230; <a title=\"How to Use the Microblaze Micro Controller System from LabVIEW\" class=\"read-more\" href=\"https:\/\/fpganow.com\/index.php\/2017\/06\/23\/how-to-use-the-microblaze-micro-controller-system-from-labview\/\" aria-label=\"Read more about How to Use the Microblaze Micro Controller System from LabVIEW\">Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","footnotes":""},"categories":[7,6],"tags":[],"class_list":["post-126","post","type-post","status-publish","format-standard","hentry","category-fpga","category-labview","masonry-post","generate-columns","tablet-grid-50","mobile-grid-100","grid-parent","grid-50"],"_links":{"self":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/126","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/comments?post=126"}],"version-history":[{"count":25,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/126\/revisions"}],"predecessor-version":[{"id":262,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/126\/revisions\/262"}],"wp:attachment":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/media?parent=126"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/categories?post=126"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/tags?post=126"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}