LabVIEW FPGA has an IP Export tool that you can use to bring vi’s from LabVIEW in to your custom design in Vivado.\u00a0 One constraint is that you can only use LabVIEW FPGA primitives, or put another way – logic that stays inside the FPGA, meaning you cannot write to DRAM or access some other IO pins on the NI board you are developing your LabVIEW FPGA IP for.<\/p>\n
The other constraint is that the FPGA that your LabVIEW FPGA project lives in has to be of the same family as the board you intend to bring the IP to.<\/p>\n
Up until now I was not aware of any National Instruments boards that use an FPGA from the AMD Versal family and when I recently learned about the PXIe-8290 SmartNIC<\/strong> <\/em>I got excited.\u00a0 At $61,852.00 USD<\/strong> <\/em><\/span>that board is outside of my “hobbyist” budget and I decided to find the cheapest AMD Versal board that I could find and I found one for just under $1,000 USD<\/strong> <\/em><\/span>from a German company called Trenz Electronics<\/strong><\/a>.<\/p>\n The TE0950, by Trenz Electronics comes with an VE2202, VE2302, or VM1102 AMD Versal FPGA, DDR4 SDRAM, and a zQSFP connector.\u00a0 Now the zQSFP is problematic for me because my 10 Gigabit connector is the QNA-T310G1S Thunderbolt to 10GbE SFP+ connector and it is not compatible unless I use the TEF0008-03-D to break out the zQSFP to have 4 compatible ports.\u00a0 I will have to do some more reading and research before I get that option working.\u00a0 Anyway, for now here are the links to all the pieces I just mentioned:<\/p>\n NI PXIe-8290:<\/strong><\/p>\n QNAP<\/strong><\/p>\n TE0950<\/strong><\/p>\n TEF0008-03-D<\/strong><\/p>\n LabVIEW FPGA has an IP Export tool that you can use to bring vi’s from LabVIEW in to your custom design in Vivado.\u00a0 One constraint is that you can only use LabVIEW FPGA primitives, or put another way – logic that stays inside the FPGA, meaning you cannot write to DRAM or access some other … Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","footnotes":""},"categories":[1],"tags":[],"class_list":["post-19965","post","type-post","status-publish","format-standard","hentry","category-uncategorized","masonry-post","generate-columns","tablet-grid-50","mobile-grid-100","grid-parent","grid-50"],"_links":{"self":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/19965","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/comments?post=19965"}],"version-history":[{"count":4,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/19965\/revisions"}],"predecessor-version":[{"id":19974,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/19965\/revisions\/19974"}],"wp:attachment":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/media?parent=19965"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/categories?post=19965"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/tags?post=19965"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}\n
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