Additionally, this example can be run in multiple ways, all from the command line or by using the Vitis User Interface:<\/p>\n\n\n\n
- \n
- Bare-Metal<\/li>\n\n\n\n
- FreeRTOS\n
- \n
- https:\/\/www.freertos.org\/<\/a><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\n
If you are a beginner, I hope this saves you a lot of time.<\/p>\n\n\n\n
Getting Started<\/h2>\n\n\n\n
1 – Download and Install:<\/h3>\n\n\n\n
- \n
- Vivado 2024.1\n
- \n
- https:\/\/www.xilinx.com\/support\/download\/index.html\/content\/xilinx\/en\/downloadNav\/vivado-design-tools\/2024-1.html<\/a><\/li>\n<\/ul>\n<\/li>\n\n\n\n
- Vitis 2024.1\n
- \n
- https:\/\/www.xilinx.com\/support\/download\/index.html\/content\/xilinx\/en\/downloadNav\/vitis\/2024-1.html<\/a><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\n
2 – Connect your Arty Z7-20 to your machine via USB<\/h3>\n\n\n\n
![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-36.png\")
<\/figure>\n\n\n\n3 – Clone the Git Repository<\/h3>\n\n\n\n
mkdir -p ~\/work\/artyz7\ncd ~\/work\/artyz7\ngit clone git@github.com:FpgaJohn\/arty_hw.git<\/code><\/pre>\n\n\n\nManual Recreation of Project<\/h2>\n\n\n\n
NOTE:<\/strong><\/em> You must set the Arty Z7-20 jumper to JTAG, otherwise the commands will not work out-of-the box:<\/span><\/p>\n\n\n\n
![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-35.png\")
<\/figure>\n\n\n\n1 – Open Vivado and Recreate Block Design<\/h3>\n\n\n\n
# Source Vivado Tools\n . \/tools\/Xilinx\/Vivado\/2024.1\/settings64.sh\n\n# Launch Vivado\nvivado &<\/code><\/pre>\n\n\n\nFind the TCL Console at the bottom of Vivado, and navigate to the arty_hw\/vivado directory and source the arty_hw.tcl TCL script.<\/p>\n\n\n\n
cd .\/arty_hw\/vivado\nsource .\/arty_hw.tcl<\/code><\/pre>\n\n\n\n![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-2.png\")
<\/figure>\n\n\n\nInspect the block design and you will see:<\/p>\n
- \n
- A Dual channel GPIO with all Outputs set and connected to a custom IP Block named “my_state”<\/li>\n
- A Dual channel GPIO with all Inputs set and connected to the output of the same custom IP Block named “my_state”<\/li>\n
- An AXI-Stream FIFO (4.3) configured to use AXI4-Lite as its interface and whose TXD is connected to its RXD port<\/li>\n
- An AXI Direct Memory Access (7.1) IP Block configured with all vanilla options, that is without scatter gather mode that does not allow unaligned writes\n
- \n
- If you follow the S_AXIS_S2MM and the M_AXIS_MM2S ports you will see that they are both connected to the same AXI4-Stream Data FIFO (2.0).\u00a0 This too is also configured to be 32-bits wide, see the TDATA width value which is set to 4 bytes.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\n
2 – Synthesize, implement and generate the bitstream<\/h3>\n\n\n\n
In the bottom left of the Vivado window click on the “Generate Bitstream” and wait for it to complete.\u00a0 You can always check the TCL Console to see it progress through its various stages.<\/p>\n\n\n\n
![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-3.png\")
<\/figure>\n\n\n\nWhen the bitstream has been generated you will see the following window, just click cancel.<\/p>\n\n\n\n
![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-5.png\")
<\/figure>\n\n\n\n3 – Export the XSA file<\/h3>\n\n\n\n
Now export the bitstream:<\/p>\n
- \n
- Clicking “File->Export->Export Hardware”.<\/li>\n
- Select “Include bitstream”<\/li>\n
- Update the file name to arty_hw<\/strong>, and the directory to be the parent directory ~\/work\/arty_z7\/arty_hw\/vivado<\/strong> (see screenshot below)\n
- \n
- This will allow the Makefile to be able to find the xsa file in case you want to run the apps via the Makefile in the future.<\/li>\n<\/ul>\n<\/li>\n
- vivado\/arty_hw.xsa<\/li>\n<\/ul>\n\n\n\n
![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-6.png\")
<\/figure>\n\n\n\n![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-8.png\")
<\/figure>\n\n\n\n![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-9.png\")
<\/figure>\n\n\n\n4 – Start Vitis<\/h3>\n\n\n\n
You can exit from Vivado if you wish. Regardless, you will have to source the Vitis tools and then start Vitis in classic mode from inside the apps \/vitis directory. You will have to create the vitis directory and set that directory to be your workspace path.<\/p>\n\n\n\n
# Source the Vitis Tools\n. \/tools\/Xilinx\/Vitis\/2024.1\/settings64.sh\n\n# Create a workspace directory named vitis\ncd ~\/work\/artyz7_arty_hw\/apps\nmkdir vitis\n\n# Start Vitis 2024.1 in Classic Mode\nvitis --classic &<\/code><\/pre>\n\n\n\n![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-10.png\")
<\/figure>\n\n\n\n5 – Create Platform Project<\/h3>\n\n\n\n
- \n
- Click “File->New->Platform Project”<\/li>\n
- Name the project plat_bm<\/li>\n
- Browse to and select the XSA file from the previous step<\/li>\n
- No need to change anything else, click Finish<\/li>\n
- Right click on the project and select Build<\/li>\n<\/ul>\n\n\n\n
![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-11.png\")
<\/figure>\n\n\n\n6 – Create C Application with Board Support Project<\/h3>\n\n\n\n
Create a C Application:<\/p>\n
- \n
- Click File->New->New Application<\/strong><\/li>\n
- Make sure plat_bm<\/strong> is selected as the Platform<\/li>\n
- Name the project c_hw<\/strong><\/li>\n
- The defaults should be fine until you reach the Templates window\n
- \n
- Select “Empty C Application”<\/strong> <\/li>\n<\/ul>\n<\/li>\n
- Click Finish<\/li>\n<\/ul>\n
Now import the sources:<\/p>\n
- \n
- Right click on src and select “Import Sources”<\/li>\n
- Browse to the ~\/work\/artyz7\/arty_hw\/app\/arty_hw_bm directory and select <\/span>Open<\/strong><\/li>\n
- Check the following files:\n
- \n
- main.c<\/li>\n
- mmio.c<\/li>\n
- mmio.h<\/li>\n<\/ul>\n<\/li>\n
- Right click on the c_hw application and select Build<\/li>\n<\/ul>\n\n\n\n
![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-12.png\")
<\/figure>\n\n\n\n7 – Run Bare-Metal Application in Debug Mode<\/h3>\n\n\n\n
Right click on the project “c_hw” and select “Debug As-> Debug Configurations…”<\/p>\n\n\n\n
![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-20-1024x653.png\")
<\/figure>\n\n\n\nClick on the left most icon to add a new configuration under “Single Application Debug”<\/p>\n\n\n\n
![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-21.png\")
<\/figure>\n\n\n\nThis should not be an issue for most users, but it is in my case since I have multiple FPGA boards plugged in. Go to “Target Setup” And make sure that the PL Device and PS Device options are both pointing to the Digilent Arty Z7.<\/p>\n\n\n\n
![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-22-1024x531.png\")
<\/figure>\n\n\n\n![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-13.png\")
<\/figure>\n\n\n\n![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-24.png\")
<\/figure>\n\n\n\nHit Debug and monitor the console<\/p>\n\n\n\n
![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-25-1024x532.png\")
<\/figure>\n\n\n\nThen connect the Vitis Serial Terminal to the appropriate port and view the output:<\/p>\n\n\n\n
![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-26.png\")
<\/figure>\n\n\n\n![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-27.png\")
<\/figure>\n\n\n\n8 – Create FreeRTOS App<\/h3>\n\n\n\n
Now you are going to have to create another Application Project with a new Domain that supports FreeRTOS.<\/p>\n\n\n\n
Click “File->New->Application Project”<\/p>\n
Select your existing Platform project (plat_bm)<\/p>\n
Name the project c_hw_rtos<\/p>\n
Create a new domain and set the Operating System to “freertos10_xilinx”<\/p>\n\n\n\n
![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-29.png\")
<\/figure>\n\n\n\nSelect FreeRTOS Hello World<\/p>\n\n\n\n
![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-30.png\")
<\/figure>\n\n\n\nImport the same 3 files as before:<\/p>\n
- \n
- main.c<\/li>\n
- mmio.c<\/li>\n
- mmio.h<\/li>\n<\/ul>\n\n\n\n
9 – Run FreeRTOS App<\/h3>\n\n\n\n
Create a Debug Configuration like before and run the application<\/p>\n\n\n\n
![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-31-1024x664.png\")
<\/figure>\n\n\n\nThe output should be different, notice the “xTaskCreate” and “vTaskStartScheduler” function calls:<\/p>\n\n\n\n
![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-32.png\")
<\/figure>\n\n\n\n![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-33.png\")
<\/figure>\n\n\n\nAutomated – Linux Only<\/h2>\n\n\n\n
1 – Build the Bitstream and XSA<\/h3>\n\n\n\n
Now for the fun part. With the help of Claude I wrote a bunch of Makefile rules\/recipes that will automate everything done in the Manual mode. Simple, just run make and check the help menu.<\/p>\n\n\n\n
john@asus:~\/work\/artyz7\/arty_hw$ make\narty_hw \u2014 Arty Z7-20 hardware test suite\n\nVivado:\n make xsa Build Vivado project and export XSA (25-35 min)\n make xsa-clean Remove Vivado project and build artifacts\n\nBare-metal (JTAG):\n make bare-metal-build Build standalone ELF (ps7_cortexa9_0, via xsct)\n make bare-metal-run Program PL + run ELF via JTAG, capture UART\n make bare-metal-clean Remove bare-metal Vitis workspace\n\nFreeRTOS (JTAG):\n make rtos-build Build FreeRTOS ELF (ps7_cortexa9_0, via xsct)\n make rtos-run Program PL + run ELF via JTAG, capture UART\n make rtos-clean Remove FreeRTOS Vitis workspace\n\nLinux (PetaLinux board via SSH):\n make deploy Cross-compile and scp test app to board\n make deploy-run Deploy + run test app on board via SSH\n\nSetup:\n make fetch-board-parts Fetch Digilent board files into Vivado 2024.1 xhub\n\nUtilities:\n make tty Open Arty Z7 PS-UART in screen (115200 8N1)\n make tty-list List screen sessions and processes holding any \/dev\/ttyUSB*\n make tty-kill Kill any screen\/process holding the Arty Z7 PS-UART\n make board-reset System-reset the Arty Z7 PS+PL via JTAG (xsct rst -system)\n make help Show this help\n\nVariables:\n ARTY_HOST=arty Board hostname\/IP for SSH deploy\n ARTY_USER=petalinux Board username\n ARTY_UART=\/dev\/ttyUSB4 PS-UART device (auto-detected)<\/code><\/pre>\n\n\n\nYou can tinker and see what boards are connected to your system. In my case I have the Arty Z7-20<\/strong> and the Kria KR260<\/strong>:<\/p>\n\n\n\n
john@asus:~\/work\/artyz7\/arty_hw$ make list-all\n==> USB serial ports:\n \/dev\/ttyUSB1 usb=3-2 if=01 Xilinx KR Carrier Card serial=XFL1GRCZBY0R\n \/dev\/ttyUSB2 usb=3-2 if=02 Xilinx KR Carrier Card serial=XFL1GRCZBY0R\n \/dev\/ttyUSB3 usb=3-2 if=03 Xilinx KR Carrier Card serial=XFL1GRCZBY0R\n \/dev\/ttyUSB4 usb=3-3 if=01 Digilent Digilent Adept USB Device serial=003017B7EAFD\n==> JTAG scan chains (xsct):\n cable: Digilent Arty Z7 003017B7EAFDA\n device: arm_dap\n device: xc7z020\n cable: Xilinx SCK-KR XFL1GRCZBY0RA\n device: xck26\n device: arm_dap<\/code><\/pre>\n\n\n\nAnd you can see which one is for your board. In this case we know it it \/dev\/ttyUSB4, but we can be more explicit by calling “make tty-list”<\/p>\n\n\n\n
john@asus:~\/work\/artyz7\/arty_hw$ make tty-list\n==> screen sessions:\n (none)\n==> \/dev\/ttyUSB* holders:\n (none)\n==> Arty Z7 PS-UART (auto-detected): \/dev\/ttyUSB4<\/code><\/pre>\n\n\n\n2 – Prerequisite – Build the XSA<\/h3>\n\n\n\n
Just run make xsa. It took 13 minutes on my ASUS ExpertCenter PN65<\/p>\n
- \n
- https:\/\/www.asus.com\/us\/displays-desktops\/mini-pcs\/pn-series\/asus-expertcenter-pn65\/<\/a><\/li>\n<\/ul>\n\n\n\n
john@asus:~\/work\/artyz7\/arty_hw$ time make xsa\nmake -C vivado xsa\n. \/tools\/Xilinx\/Vivado\/2024.1\/settings64.sh && JOBS=1 vivado -mode batch -nojournal -log build.log -source build.tcl\n\n****** Vivado v2024.1 (64-bit)\n **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024\n **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024\n **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024\n **** Start of session at: Thu Jun 4 14:44:27 2026\n ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.\n ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n...\n----\n# puts \"Wrote XSA: [file normalize arty_hw.xsa]\"\nWrote XSA: \/home\/john\/work\/artyz7\/arty_hw\/vivado\/arty_hw.xsa\nINFO: [Common 17-206] Exiting Vivado at Thu Jun 4 14:59:46 2026...\n\nreal 13m11.710s\nuser 9m9.382s\nsys 0m26.627s<\/code><\/pre>\n\n\n\n3 – Build and Run the Bare-Metal Application<\/h3>\n\n\n\n
Now run “make bare-metal-build” and then “make bare-metal-run”, all output (for 10 seconds) will be captured and printed to the console<\/p>\n\n\n\n
john@asus:~\/work\/artyz7\/arty_hw$ make bare-metal-run\nmake -C apps\/arty_hw_bm run\n==> Configuring \/dev\/ttyUSB4 (115200 8N1)\n==> Programming PL + downloading ELF via xsct load.tcl\nattempting to launch hw_server\n\n****** Xilinx hw_server v2024.1\n **** Build date : May 16 2024 at 12:16:21\n ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.\n ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n\nINFO: hw_server application started\nINFO: Use Ctrl-C to exit hw_server application\n\nINFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121\n\nload.tcl: ELF running. UART output on ttyUSB at 115200 8N1.\n==> ELF running -- capturing UART for 10s\n\n==> Captured output (saved to bm.log):\n------------------------------------------------\n...\n----- [mmio] AXI DMA echo (mem->MM2S->S2MM->mem) -----\n tx PA=0x00112880 rx PA=0x00113880 size=4096 B\n after reset: MM2S SR=0x00000001 S2MM SR=0x00000001\n MM2S done after 37 polls, SR=0x00001002\n S2MM done after 0 polls, SR=0x00001002\n tx[0,1]=0xA0000000,0xA0000001 tx[1022,1023]=0xA00003FE,0xA00003FF\n rx[0,1]=0xA0000000,0xA0000001 rx[1022,1023]=0xA00003FE,0xA00003FF\n DMA echo: PASS (4096 bytes round-tripped)\n\n=========================================\nRESULT: ALL PASS -- 0 failures\n=========================================\n------------------------------------------------<\/code><\/pre>\n\n\n\n4 – Build and Run the FreeRTOS Application<\/h3>\n\n\n\n
There are similar commands for the rtos version. Run “make rtos-build” and “make rtos-run”:<\/p>\n\n\n\n
john@asus:~\/work\/artyz7\/arty_hw$ make rtos-run\nmake -C apps\/arty_hw_rtos run\n==> Configuring \/dev\/ttyUSB4 (115200 8N1)\n==> Programming PL + downloading ELF via xsct load.tcl\nattempting to launch hw_server\n\n****** Xilinx hw_server v2024.1\n **** Build date : May 16 2024 at 12:16:21\n ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.\n ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n\nINFO: hw_server application started\nINFO: Use Ctrl-C to exit hw_server application\n\nINFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121\n...\n----- [mmio] AXI Stream FIFO loopback (PG080) -----\n post-reset: TX vacancy=508 words\n writing 4 words to TX FIFO...\n tx[0] = 0xDEADBEEF\n tx[1] = 0xCAFEBABE\n tx[2] = 0x12345678\n tx[3] = 0xAABBCCDD\n RX occupancy=4 words, RLR=16 bytes (4 words)\n received 4 words:\n rx[0] = 0xDEADBEEF OK\n rx[1] = 0xCAFEBABE OK\n rx[2] = 0x12345678 OK\n rx[3] = 0xAABBCCDD OK\n FIFO echo: PASS\n\n----- [mmio] AXI DMA echo (mem->MM2S->S2MM->mem) -----\n tx PA=0x0011E880 rx PA=0x0011F880 size=4096 B\n MM2S done after 37 polls, SR=0x00001002\n S2MM done after 0 polls, SR=0x00001002\n tx[0,1]=0xA0000000,0xA0000001 tx[1022,1023]=0xA00003FE,0xA00003FF\n rx[0,1]=0xA0000000,0xA0000001 rx[1022,1023]=0xA00003FE,0xA00003FF\n DMA echo: PASS (4096 bytes round-tripped)\n\n=========================================\nRESULT: ALL PASS -- 0 failures\n=========================================\n------------------------------------------------<\/code><\/pre>\n\n\n\nMiscellaneous<\/h2>\n\n\n\n
Enumerate all connected boards<\/h3>\n\n\n\n
I added a utility recipe \/ rule to list all connected FPGA boards. For this portion of this article, I connected 3 total boards:<\/p>\n
- \n
- Kria KR260<\/li>\n
- ArtyZ7-20<\/li>\n
- Arty A7-100T<\/li>\n<\/ul>\n
<\/p>\n\n\n\n
john@asus:~\/work\/artyz7\/arty_hw$ make list-all\n==> USB serial ports:\n \/dev\/ttyUSB0 usb=3-4 if=00 Digilent Digilent USB Device serial=210319AFEEC7\n \/dev\/ttyUSB1 usb=3-2 if=01 Xilinx KR Carrier Card serial=XFL1GRCZBY0R\n \/dev\/ttyUSB2 usb=3-2 if=02 Xilinx KR Carrier Card serial=XFL1GRCZBY0R\n \/dev\/ttyUSB3 usb=3-2 if=03 Xilinx KR Carrier Card serial=XFL1GRCZBY0R\n \/dev\/ttyUSB4 usb=3-3 if=01 Digilent Digilent Adept USB Device serial=003017B7EAFD\n \/dev\/ttyUSB5 usb=3-4 if=01 Digilent Digilent USB Device serial=210319AFEEC7\n==> JTAG scan chains (xsct):\n cable: Digilent Arty A7-100T 210319AFEEC7A\n device: xc7a100t\n cable: Digilent Arty Z7 003017B7EAFDA\n device: arm_dap\n device: xc7z020\n cable: Xilinx SCK-KR XFL1GRCZBY0RA\n device: xck26\n device: arm_dap<\/code><\/pre>\n\n\n\nReboot the Board<\/h3>\n\n\n\n
When playing around with Linux (Ubuntu) or PetaLinux, I sometimes want to reboot the boad without having to unplug it and plug it back in (or by pressing the reset button).<\/p>\n
What I do is (using tmux) I run “make tty” to listen to the serial port interface from one window, and then from another I run “make board-reset” and I can watch the tty window reset. In my case I switched by Dip switch back to SD card and can watch it boot up to Ubuntu:<\/p>\n\n\n\n
<\/p>\n\n\n\n
![\"\"](\"https:\/\/fpganow.com\/wp-content\/uploads\/2026\/06\/image-34-1024x644.png\")
<\/figure>\n\n\n\n\n\n<\/p>\n","protected":false},"excerpt":{"rendered":"
I wanted to create a project suitable for beginners that does more than your average hello world sample out there on the internet. The project I created that will be described on this page and will show you how to run an augmented hello world that includes: Additionally, this example can be run in multiple … Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","footnotes":""},"categories":[1],"tags":[],"class_list":["post-19976","post","type-post","status-publish","format-standard","hentry","category-uncategorized","masonry-post","generate-columns","tablet-grid-50","mobile-grid-100","grid-parent","grid-50"],"_links":{"self":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/19976","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/comments?post=19976"}],"version-history":[{"count":41,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/19976\/revisions"}],"predecessor-version":[{"id":20057,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/19976\/revisions\/20057"}],"wp:attachment":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/media?parent=19976"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/categories?post=19976"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/tags?post=19976"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
- https:\/\/www.asus.com\/us\/displays-desktops\/mini-pcs\/pn-series\/asus-expertcenter-pn65\/<\/a><\/li>\n<\/ul>\n\n\n\n
- Check the following files:\n
- Click Finish<\/li>\n<\/ul>\n
- Make sure plat_bm<\/strong> is selected as the Platform<\/li>\n
- Click File->New->New Application<\/strong><\/li>\n
- If you follow the S_AXIS_S2MM and the M_AXIS_MM2S ports you will see that they are both connected to the same AXI4-Stream Data FIFO (2.0).\u00a0 This too is also configured to be 32-bits wide, see the TDATA width value which is set to 4 bytes.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\n
- Vitis 2024.1\n
- https:\/\/www.xilinx.com\/support\/download\/index.html\/content\/xilinx\/en\/downloadNav\/vivado-design-tools\/2024-1.html<\/a><\/li>\n<\/ul>\n<\/li>\n\n\n\n
- Vivado 2024.1\n
- https:\/\/www.freertos.org\/<\/a><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\n