{"id":290,"date":"2018-01-23T03:26:22","date_gmt":"2018-01-23T03:26:22","guid":{"rendered":"http:\/\/fpganow.com\/?p=290"},"modified":"2018-01-23T03:26:22","modified_gmt":"2018-01-23T03:26:22","slug":"10-gigabit-fpga-based-network-code-coming-soon","status":"publish","type":"post","link":"https:\/\/fpganow.com\/index.php\/2018\/01\/23\/10-gigabit-fpga-based-network-code-coming-soon\/","title":{"rendered":"10 Gigabit FPGA-based Network Code Coming Soon"},"content":{"rendered":"<p>I am getting real close to finishing my proof-of-concept FPGA-based network card that is based on the PXIe-6592 National Instruments Board which uses the Kinex-7 410t FPGA chip by Xilinx, and has 2GB of DDR3 RAM.<\/p>\n<p>Using the Arty Arix board, I was able to make sure that the MicroBlaze code running the lwIP TCP\/IP stack works fine, and I was able to use a NI example to make the 10 Gigabit Ethernet MAC part.\u00a0 Only issue is that the NI code is quite complex and uses features and ideas that I have never seen before.<\/p>\n<p>Nevertheless, I am iterating over some modifications to the example to allow for a LabVIEW Host network stack that uses the FPGA only for the sending and receiving of ethernet frames.\u00a0 Once I get that working, I will just switch the connection from LabVIEW Host to the on-board MicroBlaze.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>I am getting real close to finishing my proof-of-concept FPGA-based network card that is based on the PXIe-6592 National Instruments Board which uses the Kinex-7 410t FPGA chip by Xilinx, and has 2GB of DDR3 RAM. Using the Arty Arix board, I was able to make sure that the MicroBlaze code running the lwIP TCP\/IP &#8230; <a title=\"10 Gigabit FPGA-based Network Code Coming Soon\" class=\"read-more\" href=\"https:\/\/fpganow.com\/index.php\/2018\/01\/23\/10-gigabit-fpga-based-network-code-coming-soon\/\" aria-label=\"Read more about 10 Gigabit FPGA-based Network Code Coming Soon\">Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","footnotes":""},"categories":[1],"tags":[],"class_list":["post-290","post","type-post","status-publish","format-standard","hentry","category-uncategorized","masonry-post","generate-columns","tablet-grid-50","mobile-grid-100","grid-parent","grid-50"],"_links":{"self":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/290","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/comments?post=290"}],"version-history":[{"count":1,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/290\/revisions"}],"predecessor-version":[{"id":291,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/290\/revisions\/291"}],"wp:attachment":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/media?parent=290"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/categories?post=290"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/tags?post=290"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}