{"id":317,"date":"2018-02-13T01:45:09","date_gmt":"2018-02-13T01:45:09","guid":{"rendered":"http:\/\/fpganow.com\/?p=317"},"modified":"2018-02-13T01:48:00","modified_gmt":"2018-02-13T01:48:00","slug":"ip-integration-node-vs-clip","status":"publish","type":"post","link":"https:\/\/fpganow.com\/index.php\/2018\/02\/13\/ip-integration-node-vs-clip\/","title":{"rendered":"IP Integration Node vs CLIP"},"content":{"rendered":"<p>I wired up the 10 gigabit ethernet MAC to my MicroBlaze instance to my host computer and compiled\/synthesized everything.\u00a0 I then turn on my &#8220;quiet&#8221; PXIe-1062Q and fire up my tester application and it did not work&#8230;\u00a0 I open up an isolated tester &#8211; &#8220;Fpga-Mac-Top.vi&#8221;, and it worked.\u00a0 I open up the isolated MicroBlaze tester &#8211; &#8220;Fpga-MicroBlaze-Top.vi&#8221;, and nothing.\u00a0 Not even a read from the GPIO.<\/p>\n<p>This is quite strange&#8230; why is it not working? I spend some time looking over everything, re-generating output products, synthesizing from Vivado, bringing the design back in to LabVIEW, and long story short I was not setting the MicroBlaze Reset to ACTIVE_LOW, whereas in all of my previous designs I was setting it to ACTIVE_HIGH.\u00a0 Anyway, while I wait for it to compile, I have something to say.\u00a0 Which do you prefer? Using an IP Integration Node or a CLIP (Component Level IP) for using a MicroBlaze Processor from LabVIEW?<\/p>\n<p>Well, first off, let me link to some National Instruments documentation on both:<\/p>\n<ul class=\"ili-indent\">\n<li>Importing External IP into LabVIEW FPGA:\n<ul>\n<li><a href=\"http:\/\/www.ni.com\/tutorial\/7444\/en\/\">http:\/\/www.ni.com\/tutorial\/7444\/en\/<\/a><\/li>\n<\/ul>\n<\/li>\n<li>Using VHDL Code as Component-Level IP\n<ul>\n<li><a href=\"http:\/\/zone.ni.com\/reference\/en-XX\/help\/371599N-01\/lvfpgaconcepts\/using_component_ip\/\">http:\/\/zone.ni.com\/reference\/en-XX\/help\/371599N-01\/lvfpgaconcepts\/using_component_ip\/<\/a><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>And now let me show you some screen shots.\u00a0 Here is a close up of what using an IP Integration Node looks like: (right-click to open in a new window for a larger version until I figure out how to modify this wordpress theme to be wider)<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/02\/IP-Integration-Node.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-318\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/02\/IP-Integration-Node.png\" alt=\"\" width=\"800\" height=\"605\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/02\/IP-Integration-Node.png 563w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/02\/IP-Integration-Node-300x227.png 300w\" sizes=\"auto, (max-width: 800px) 100vw, 800px\" \/><\/a><\/p>\n<p>Here is a zoomed out version of this same VI:<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/02\/MicroBlaze-with-IP-Node.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-319\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/02\/MicroBlaze-with-IP-Node.png\" alt=\"\" width=\"1500\" height=\"1078\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/02\/MicroBlaze-with-IP-Node.png 1385w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/02\/MicroBlaze-with-IP-Node-300x216.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/02\/MicroBlaze-with-IP-Node-768x552.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/02\/MicroBlaze-with-IP-Node-1024x736.png 1024w\" sizes=\"auto, (max-width: 1500px) 100vw, 1500px\" \/><\/a><\/p>\n<p>And finally, what it looks like without an IP Integration node, but with a CLIP (Component Level-IP):<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/02\/MicroBlaze-with-CLIP.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-320\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/02\/MicroBlaze-with-CLIP.png\" alt=\"\" width=\"1500\" height=\"1068\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/02\/MicroBlaze-with-CLIP.png 1306w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/02\/MicroBlaze-with-CLIP-300x214.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/02\/MicroBlaze-with-CLIP-768x547.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/02\/MicroBlaze-with-CLIP-1024x729.png 1024w\" sizes=\"auto, (max-width: 1500px) 100vw, 1500px\" \/><\/a><\/p>\n<p>&nbsp;<\/p>\n<p>Can you see the difference? I can&#8230; for starters, I can read the full name of each signal when using a CLIP.\u00a0 Additionally, with a CLIP I can split up my nodes in to separate locations, so that I can organize my VI in a much cleaner way.\u00a0 And finally, since I can read the full signal name when using a CLIP node, I no longer have to hover over each signal to get the signal name, thus removing any reason for having comments as in the IP Integration Node version.<\/p>\n<p>Anyway.\u00a0 CLIP node is my recommended method of using LabVIEW FPGA to import Xilinx Vivado IP.<\/p>\n<p>Also, this code was from a project that I implemented in order to learn how to use the AXI Stream FIFO inside of LabVIEW via a MicroBlaze.\u00a0 In other words, how to communicate with a MicroBlaze processor via an AXI Stream FIFO from LabVIEW FPGA.<\/p>\n<p>See the source code here:<\/p>\n<p><a href=\"https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/tree\/master\/06_MicroBlaze\/03_MicroBlaze_AXI_Stream\">https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/tree\/master\/06_MicroBlaze\/03_MicroBlaze_AXI_Stream<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>I wired up the 10 gigabit ethernet MAC to my MicroBlaze instance to my host computer and compiled\/synthesized everything.\u00a0 I then turn on my &#8220;quiet&#8221; PXIe-1062Q and fire up my tester application and it did not work&#8230;\u00a0 I open up an isolated tester &#8211; &#8220;Fpga-Mac-Top.vi&#8221;, and it worked.\u00a0 I open up the isolated MicroBlaze tester &#8230; <a title=\"IP Integration Node vs CLIP\" class=\"read-more\" href=\"https:\/\/fpganow.com\/index.php\/2018\/02\/13\/ip-integration-node-vs-clip\/\" aria-label=\"Read more about IP Integration Node vs CLIP\">Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","footnotes":""},"categories":[11,7,12,6],"tags":[],"class_list":["post-317","post","type-post","status-publish","format-standard","hentry","category-clip","category-fpga","category-ipnode","category-labview","masonry-post","generate-columns","tablet-grid-50","mobile-grid-100","grid-parent","grid-50"],"_links":{"self":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/317","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/comments?post=317"}],"version-history":[{"count":4,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/317\/revisions"}],"predecessor-version":[{"id":324,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/317\/revisions\/324"}],"wp:attachment":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/media?parent=317"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/categories?post=317"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/tags?post=317"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}