{"id":340,"date":"2018-02-16T02:42:43","date_gmt":"2018-02-16T02:42:43","guid":{"rendered":"http:\/\/fpganow.com\/?p=340"},"modified":"2018-02-16T13:50:22","modified_gmt":"2018-02-16T13:50:22","slug":"coding-standards-matter","status":"publish","type":"post","link":"https:\/\/fpganow.com\/index.php\/2018\/02\/16\/coding-standards-matter\/","title":{"rendered":"Coding Standards Matter…"},"content":{"rendered":"

I have wired up the components of my 10 Gigabit FPGA Accelerated Network card with great care, and I decided to have my “tester” application skip the lwIP stack and to pass the received packet directly to the host for testing\/verification purposes.<\/p>\n

Everything was checking out fine, the LabVIEW code looked flawless, the interface to the 10 Gigabit Transceiver was perfect.\u00a0 All looked fine, but for some reason I was not receiving the packets on the host.<\/p>\n

I analyzed the code, inserted probes and what not.\u00a0 And finally, I was reading through the actual C++ code (MicroBlaze C++ that is) I found the bug.<\/p>\n

A very simple bug hidden in plain sight!<\/p>\n

\n

\/\/ Now echo the data back out
\nif (XLlFifo_iTxVacancy(fifo_1)) {
\nXGpio_DiscreteWrite(&gpio_2, 2, 0xF001);
\nfor ( i = 0; i < recv_len_bytes; i++) {
\nXGpio_DiscreteWrite(&gpio_2, 2, buffer[i]);<\/p>\n

XLlFifo_Write(fifo_1, buffer, recv_len_bytes);<\/p>\n

}<\/p>\n

XLlFifo_iTxSetLen(fifo_1, recv_len_bytes);
\n}<\/p>\n

\n

Do you see the error?\u00a0 Well, neither did I, until I read the documentation for XLlFifo_Write again, for the umteenth time… I was writing the data of the packet to the buffer (length of packet) squared times! Why? Because the single call to XLlFifo_Write is writing the entire packet on each call.<\/p>\n

Anyway, I am now re-synthesizing my code and we will see what happens when I run it in around 2 hours time.<\/p>\n

Also, I added the TKEEP signal to my AXI Stream FIFO, and it worked exactly as expected, meaning that:<\/p>\n