![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/03\/30000-Foot-Overview.png\")
<\/a><\/p>\n- \n
- There are four (4) 10 Gigabit ports available on this device, but I am using only one of them for this design.<\/li>\n
- The FPGA design contains a MicroBlaze soft-core Processor<\/li>\n
- This MicroBlaze soft-core Processor is connected to a LabVIEW for Windows Executable, which is the same thing as a standard .exe file.<\/li>\n<\/ul>\n
Now some more details:<\/p>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/03\/More-Details.png\")
<\/a><\/p>\n- \n
- Any type of Ethernet Frame can enter the 10 Gigabit PHY, as shown in the diagram:\n
- \n
- An Ethernet Frame with an ARP Request<\/li>\n
- An Ethernet Frame with an IPv4 Packet containing an ICMP packet, otherwise known as a “Ping” message<\/li>\n
- An Ethernet Frame with an IPv4 Packet containing a UDP packet.\u00a0 You may known this as “multicast” or “broadcast” messages.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n
And finally, everything, the full shebang:<\/p>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/03\/Full-shebang.png\")
<\/a>I have broken out the details of the hardware comprising the 10 Gigabit connection.\u00a0 Technically it consists of 4 SFP+ connectors going to a Multi-Gigabit Transceiver.\u00a0 Now normally I would think that there is some sort of chip in between the SFP+ and the FPGA, but I believe that National Instruments has used some Xilinx IP that handles this for us.\u00a0 See, I don’t even know what hardware is being used, but I am able to use it and make an FPGA-based Network Card!<\/em><\/p>\n<\/h2>\n
The data from the Multi-Gigabit Transceiver then goes to the 10 GE MAC Core, which sends all received packets<\/p>\n
First, a Definition<\/strong><\/p>\n
CLIP – Stands for Component Level IP and is a method of bringing in non-LabVIEW FPGA code in to LabVIEW.\u00a0 Basically you take a synthesized design, wrap it up in some VHDL and import this VHDL file to LabVIEW.\u00a0 In this case an instance of the OpenCores 10 GE Mac is being brought in to the the design.<\/p>\n
See the top-level wrapper VHDL file here:<\/p>\n
https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/blob\/master\/07_10_Gigabit_CLIP\/CLIP\/TenGbEClip.vhd<\/a><\/p>\n
See the source code of this core here:<\/p>\n
https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/tree\/master\/07_10_Gigabit_CLIP\/CLIP\/xge_mac_opencore\/source\/xge_mac_opencore<\/a><\/p>\n
See the official project website for this core here:<\/p>\n
https:\/\/opencores.org\/project,xge_mac<\/a><\/p>\n
Now the Descriptions<\/strong><\/p>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/03\/Everything-with-Annotations.png\")
<\/a><\/p>\nA<\/strong><\/span> – The reading of incoming frames is wrapped up in to a nice library by National Instruments, that even includes some IP to respond to ARP messages.\u00a0 I have stripped all of this usage out for this design because I wanted simplicity for learning.\u00a0 Anyway, on each clock cycle you have the following variables:<\/p>\n
- \n
- data valid [boolean]<\/li>\n
- data [64 bit WORD]<\/li>\n
- byte enables [array of 8 booleans]<\/li>\n
- End of Good Frame [boolean]<\/li>\n
- End of Bad Frame [boolean]<\/li>\n<\/ul>\n
Here is a screenshot of the usage for this, it should be very easy to understand once you have an idea of what LabVIEW is and how it works.<\/p>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/03\/CLIP-Incoming.png\")
<\/a><\/p>\nB<\/strong><\/span> – Now the data coming from the 10 Gigabit PHY contains 64-bit WORDs, and 2 booleans, one for a good frame, and one for a bad frame.\u00a0 Now I do not know how to configure and properly use a 64-bit AXI-Data Stream FIFO with a MicroBlaze processor, so I had to convert this data manually myself.\u00a0 It did not take long, in fact I documented this in my log where it took me 1 hour and 15 minutes to do this following the LabVIEW FPGA State Machine paradigm.\u00a0 Think of the LabVIEW FPGA State Machine paradigm or pattern as the absolute best of both worlds in terms of VHDL\/Verilog and LabVIEW.<\/p>\n
So, we have data coming in what I call “AXI-64bit format” and we have to convert it\/write it to a LabVIEW FIFO.\u00a0 Here is a close-up of this code:<\/p>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/03\/B-AXI-64-to-LabVIEW-FIFO.png\")
<\/a><\/p>\nThe code above is running inside a loop clocked at 156.25 MHz, and on the left is how we get the data from the 10 GE MAC.\u00a0 If “data valid”, or “End of Good Frame” or “End of Bad Frame” are true, we enter the self explanatory Case Structure, which is the same thing as an if statement.\u00a0 Inside this case we package all the data in to a custom “Cluster type”, which is the same thing as a C structure and write it in to a LabVIEW FIFO.<\/p>\n
C<\/strong><\/span> – Now we read one element on each clock cycle of the custom LabVIEW Cluster defined in step B, and convert this in to a 32-bit AXI Data Stream to be read by the MicroBlaze.<\/p>\n
Here is a screenshot of the entire loop, which runs at 100MHz, because I clocked my MicroBlaze to that speed.\u00a0 I could probably increase my MicroBlaze to 156.25MHz, but that will decrease my productivity in terms of longer synthesis times.
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/03\/C-Whole-Loop.png\")
<\/a><\/p>\nI zoomed out a bit further for this screenshot and included the clock specifier, which is 100 MHz.\u00a0 Also notice how there is another “Case Structure” inside this loop, but the case is not “True”, but it is a State Machine with the “Read-Top” case showing as the default state.\u00a0 This state checks if the incoming data is valid, and if so writes the upper 32 bits of the 64-bit data WORD in to the AXI-Data Stream FIFO that is connected to the MicroBlaze.<\/p>\n
Here is a close-up of the “Read-Top” state:<\/p>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/03\/C-Read-Top.png\")
<\/a><\/p>\nHere is the other state:<\/p>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/03\/C-Read-Bottom.png\")
<\/a><\/p>\nThe “Read-Bottom” state.\u00a0 This state will write the lower half of the 64-bit WORD and will check if this is the final element in the Ethernet Frame.\u00a0 If this is the final element, it will enter the “Append-Size” state, which is incorrectly named, will fix that later “TODO: Rename Append-Size”. haha.\u00a0 Anyway, it will append some metadata indicating if this frame should be dropped or kept.<\/p>\n
The final state – “Append-Size”:<\/p>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/03\/C-Append-Size.png\")
<\/a><\/p>\nThis code is very simple.\u00a0 I set TKEEP to all one’s, or 0b1111, and I set the first 2 bits of the 32-bit WORD to contain “End of Good Frame” and “End of Bad Frame”.\u00a0 Now why am I setting TKEEP to all 1’s? Well, simple, because I haven’t implemented this part yet, however, by setting it to all 1’s my code will still work because most TCP\/IP stacks just ignore all padded 0’s.<\/p>\n
D<\/strong><\/span> – Now the MicroBlaze has been programmed with a function that reads an incoming frame from AXI-Data Stream FIFO #0 and writes its contents to AXI-Data Stream FIFO #1.\u00a0 It also reads an incoming frame from AXI-Data Stream FIFO #1 and writes its contents to AXI-Data Stream FIFO #0.\u00a0 This is a simple passthrough that exercises my implementation of the FIFOs.<\/p>\n
A direct link to the source code of this C code that is running in the MicroBlaze:<\/p>\n
https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/blob\/master\/07_10_Gigabit_CLIP\/mb_lwip\/mb_lwip.sdk\/mb_lwip\/src\/helpers.c#L83<\/a><\/p>\n
And a screenshot:<\/p>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/03\/D-Source-Code.png\")
<\/a><\/p>\nE<\/strong><\/span> – Now what happens after the source code above executes? Well, data is read from the 10 Gigabit PHY and read on the first AXI-Data Stream FIFO and written out back to the rest of the FPGA via the second AXI-Data Stream FIFO.\u00a0 So we want to read this ethernet frame and write it up to the Host application running on normal\/regular Windows.\u00a0 This is very simple, read data, write data to a Target-to-Host LabVIEW FIFO, and if tlast is equal to true, include this in the metadata, which for now is simply the upper half of the 64-bit WORD.<\/p>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/03\/E-ToHost.png\")
<\/a><\/p>\nF<\/strong><\/span> – Now how do you read this data on the host? Well, if you are familiar with LabVIEW, the code would look like this:<\/p>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/03\/F-Read-from-Target.png\")
<\/a><\/p>\nThe green box contains a reference to the running FPGA.\u00a0 The first box on the left polls the FIFO to see if any elements are available, and if the number of elements available is greater than 0 it reads that number of elements.<\/p>\n
If you wanted to do this from C++, you could use LabWindows CVI to read from the FPGA interface as such:<\/p>\n
\/* read the DMA FIFO *\/
\nNiFpga_MergeStatus(&status, NiFpga_ReadFifoI16 (session,
\nNiFpga_fpga_TargetToHostFifoI16_AIFIFO,
\ndata, numSamples, timeout, &r));<\/p>\n(See: http:\/\/www.ni.com\/tutorial\/8638\/en\/<\/a>)<\/p>\n
Please note that you can also link to the LabWindows CVI library and use it from your existing C++ applications.\u00a0 Drivers for this specific board are only available for Windows, but if you are a big bank or financial firm with deep pockets, I’m sure you can set up some sort of agreement with National Instruments to port this code and drivers to <Operating System of your Choice>.<\/p>\n
Okay, that is great, now what about writing data from the Host application back to the FPGA for sending out of the 10 Gigabit PHY? Well, you do the opposite, you enter the codes in reverse. (Spies Like Us).<\/p>\n
Instead of a “Target-to-Host” FIFO, use a\u00a0 “Host-to-Target” FIFO, and in my case, I prepend the size in WORDs to the packet to be sent.<\/p>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/03\/F-ToTarget.png\")
<\/a><\/p>\nAgain, the green box is a reference to the running FPGA.\u00a0 The square light green colored box is a function, also known as a “sub-VI” that I wrote that generates a UDP packet (or is it a UDP datagram? I forget).\u00a0 The output of this UDP packet is converted in to 32-bit WORDS by the box with a white background, and then the size is prepended to this array and written in to the “HT_WRITE” LabVIEW Host-to-Target FIFO.<\/p>\n
G<\/strong><\/span> – So we are receiving data in the following format from the host:<\/p>\n
<size><\/p>\n
<WORD1><\/p>\n
<WORD2><\/p>\n
…<\/p>\n
<WORDN><\/p>\n
We read the size and then the rest of the elements from the FIFO and write them to the 2nd AXI-Data Stream FIFO that is connected to the MicroBlaze.\u00a0 Again note that I have not yet fully implemented the proper usage of the TKEEP signals, so in this case the TKEEP signal can be dynamically set from the Host application for testing purposes.<\/p>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/03\/G-Convert-LabVIEW-AXI-32.png\")
<\/a><\/p>\nH<\/strong><\/span> – Now that the MicroBlaze has read our outgoing ethernet frame on Fifo #1 and has written the same outgoing frame on FIFO #0, we have to convert this 32-bit AXI Data Stream in to 64-bit words that are suitable for our 10 Gigabit Ethernet PHY.<\/p>\n
This time however, I used a proper state machine and named all of the states correctly.<\/p>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/03\/H-Convert-AXI-to-LabVIEW-FIFO.png\")
<\/a><\/p>\nThe left-most box connects the signals from the MicroBlaze to LabVIEW and wires them in to the state machine.\u00a0 If the data is valid and it is not the last element, the top half is stored in to a shift-register and the next state is “Read-Bottom”.\u00a0 Here is a close-up of the “Read-Top” state:<\/p>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/03\/H-Read-Top.png\")
<\/a><\/p>\nAnd here is a close-up of the “Read-Bottom” state:<\/p>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/03\/H-Read-Bottom.png\")
<\/a><\/p>\nI<\/strong><\/span> – Now we have written the 32-bit data coming from the MicroBlaze in to a LabVIEW FIFO with 64-bit data WORDS and we have to write this out using the CLIP, via the National Instruments provided wrapper.<\/p>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/03\/I-Outgoing.png\")
<\/a><\/p>\nLook at how simple and beautiful this code is!<\/p>\n
You can look at the source code here: (you must clone the repository to your local machine to see it easier, just clone it and open the 2nd file – the html file)<\/p>\n
- \n
- FPGA top level\n
- \n
- https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/blob\/master\/07_10_Gigabit_CLIP\/FPGA\/FPGANic\/Fpga-FPGANic-Top.vi<\/a><\/li>\n
- https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/blob\/master\/07_10_Gigabit_CLIP\/ScreenShots\/Fpga-FPGANic-Top.html<\/a><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n
If you do now know git, you can also download a zip file of the entire repository:<\/p>\n
https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/archive\/master.zip<\/a><\/p>\n
If you somewhat know git, you can:<\/p>\n
git clone\u00a0git@github.com:JohnStratoudakis\/LabVIEW_Fpga.git<\/p>\n
And finally, browse the documentation, which is probably outdated here:<\/p>\n
https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/tree\/master\/07_10_Gigabit_CLIP<\/a><\/p>\n
Up Next<\/strong><\/p>\n
So what now? Do I continue cleaning up the code and updating documentation? Do I make a youtube video demonstrating this?\u00a0 Do I modify the MicroBlaze code to no longer just be a “passthrough” but instead to send all data through the lwIP TCP\/IP stack? If I do this, I will have to modify the elf file (compiled binary) that is embedded in to my design, breaking this design, so I can make multiple Xilinx checkpoints and it will work, but that will confuse all of my readers… Man decisions, decisions.<\/p>\n
How about this, I finalize this project, make a new sub-directory in the source code and make a brand new LabVIEW FPGA project and this time I will use the lwIP version of the source code and I will make sure that everything is reproducible.\u00a0 It is raining now anyway and I want to stay inside and code…<\/p>\n
<\/p>\n","protected":false},"excerpt":{"rendered":"
I normally avoid shop words or “corporate speak” because I feel it dehumanizes us, but sometimes these phrases are necessary.\u00a0 So here is the “30,000 foot” view.\u00a0 And please pardon the appearance of my flow charts and diagrams, I am not a graphic designer… All images open in a new tab, so just click on … Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","footnotes":""},"categories":[11,7,6,8],"tags":[],"class_list":["post-346","post","type-post","status-publish","format-standard","hentry","category-clip","category-fpga","category-labview","category-microblaze","masonry-post","generate-columns","tablet-grid-50","mobile-grid-100","grid-parent","grid-50"],"_links":{"self":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/346","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/comments?post=346"}],"version-history":[{"count":8,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/346\/revisions"}],"predecessor-version":[{"id":374,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/346\/revisions\/374"}],"wp:attachment":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/media?parent=346"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/categories?post=346"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/tags?post=346"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
- https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/blob\/master\/07_10_Gigabit_CLIP\/ScreenShots\/Fpga-FPGANic-Top.html<\/a><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n
- https:\/\/github.com\/JohnStratoudakis\/LabVIEW_Fpga\/blob\/master\/07_10_Gigabit_CLIP\/FPGA\/FPGANic\/Fpga-FPGANic-Top.vi<\/a><\/li>\n
- FPGA top level\n
- Any type of Ethernet Frame can enter the 10 Gigabit PHY, as shown in the diagram:\n