{"id":385,"date":"2018-04-03T21:15:24","date_gmt":"2018-04-03T21:15:24","guid":{"rendered":"http:\/\/fpganow.com\/?p=385"},"modified":"2018-04-03T22:00:26","modified_gmt":"2018-04-03T22:00:26","slug":"labview-fpga-microblaze-and-uart-full-guide","status":"publish","type":"post","link":"https:\/\/fpganow.com\/index.php\/2018\/04\/03\/labview-fpga-microblaze-and-uart-full-guide\/","title":{"rendered":"LabVIEW FPGA, MicroBlaze, and UART &#8211; Full Guide"},"content":{"rendered":"<p>Working from scratch, I created a LabVIEW FPGA project that imports a MicroBlaze design that communicates with LabVIEW via a UART, and has the ability to change the elf file in a much shorter time frame than before.<\/p>\n<p>I did this by adding the MicroBlaze to the project after it had been exported to Vivado, and not from within the CLIP that is imported as before.\u00a0 The only bad news is that I have to synthesize the FPGA project from Vivado, which currently is not connected to the NI FPGA Compile Cloud.\u00a0 This may be a feature that is coming soon, but it will only come if users start using this the Project Export to Vivado feature in the first place.\u00a0 So please write me any comments if anything is confusing or hard to follow below!<\/p>\n<h2>YouTube Video Demonstration<\/h2>\n<p><iframe loading=\"lazy\" title=\"Generate a LabVIEW FPGA Design with MicroBlaze and UART\" width=\"1200\" height=\"900\" src=\"https:\/\/www.youtube.com\/embed\/Sg6snrIV0T0?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture\" allowfullscreen><\/iframe><\/p>\n<p><iframe loading=\"lazy\" title=\"LabVIEW Fpga MicroBlaze Uart Run\" width=\"1200\" height=\"675\" src=\"https:\/\/www.youtube.com\/embed\/mX2Azog-9H8?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture\" allowfullscreen><\/iframe><\/p>\n<h2>Source Code<\/h2>\n<p>See my github repository here:<\/p>\n<p><a href=\"https:\/\/github.com\/JohnStratoudakis\/MicroBlaze_UART\">https:\/\/github.com\/JohnStratoudakis\/MicroBlaze_UART<\/a><\/p>\n<h1>Part 1 &#8211; Create and Export a MicroBlaze Design<\/h1>\n<p>We are creating a MicroBlaze design, settings all of our processor options, including adding an instance of the UARTlite IP core, and exporting this Block Design to a tcl script that we will later on import in to our LabVIEW FPGA generated Vivado Project.\u00a0 We will not export the hardware or create any elf files in this part.<\/p>\n<ul class=\"ili-indent\">\n<li>Create a new project from within Vivado 2015.4 (this is important, it will likely not work from other versions of Vivado)\n<ul>\n<li>\u00a0<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/01-Create-New-Project.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-388\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/01-Create-New-Project.png\" alt=\"\" width=\"195\" height=\"174\" \/><\/a><\/li>\n<\/ul>\n<\/li>\n<li>The first step is not that important, you can just click next<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-Project-Wizard-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-389\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-Project-Wizard-1.png\" alt=\"\" width=\"743\" height=\"528\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-Project-Wizard-1.png 743w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-Project-Wizard-1-300x213.png 300w\" sizes=\"auto, (max-width: 743px) 100vw, 743px\" \/><\/a><\/li>\n<li>I selected the project location to be on my E drive, &#8220;E:\/git\/MicroBlaze_UART\/xilinx_mb&#8221;, and the name of the project to be &#8220;mb_uart&#8221;.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-Project-Wizard-2.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-390\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-Project-Wizard-2.png\" alt=\"\" width=\"743\" height=\"528\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-Project-Wizard-2.png 743w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-Project-Wizard-2-300x213.png 300w\" sizes=\"auto, (max-width: 743px) 100vw, 743px\" \/><\/a><\/li>\n<li>This is an RTL project type, and we do not want to specify any sources at this time.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/04-Project-Wizard-3.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-391\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/04-Project-Wizard-3.png\" alt=\"\" width=\"743\" height=\"528\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/04-Project-Wizard-3.png 743w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/04-Project-Wizard-3-300x213.png 300w\" sizes=\"auto, (max-width: 743px) 100vw, 743px\" \/><\/a><\/li>\n<li>The PXIe-6592R board contains a Kintex-7 FPGA chip with the following parameters:\n<ul>\n<li>Part #: xc7k410tffg900-2<\/li>\n<li>Family: Kintex-7<\/li>\n<li>Package: ffg900<\/li>\n<li>Speed Grade: -2<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-Project-Wizard-4.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-392\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-Project-Wizard-4.png\" alt=\"\" width=\"743\" height=\"528\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-Project-Wizard-4.png 743w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-Project-Wizard-4-300x213.png 300w\" sizes=\"auto, (max-width: 743px) 100vw, 743px\" \/><\/a><\/li>\n<\/ul>\n<\/li>\n<li>New Project Summary, just click finish<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/06-Project-Wizard-5.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-393\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/06-Project-Wizard-5.png\" alt=\"\" width=\"743\" height=\"528\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/06-Project-Wizard-5.png 743w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/06-Project-Wizard-5-300x213.png 300w\" sizes=\"auto, (max-width: 743px) 100vw, 743px\" \/><\/a><\/li>\n<li>What an empty project looks like:<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-Empty-Project.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-394\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-Empty-Project.png\" alt=\"\" width=\"1858\" height=\"1103\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-Empty-Project.png 1858w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-Empty-Project-300x178.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-Empty-Project-768x456.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-Empty-Project-1024x608.png 1024w\" sizes=\"auto, (max-width: 1858px) 100vw, 1858px\" \/><\/a><\/li>\n<li>Now create a block design\n<ul>\n<li><a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-Create-Block-Design-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-395\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-Create-Block-Design-1.png\" alt=\"\" width=\"400\" height=\"268\" \/><\/a><\/li>\n<\/ul>\n<\/li>\n<li>I have been going with the &#8220;d_&#8221; d underscore followed by microblaze naming schema<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-Create-Block-Design-2.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-396\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-Create-Block-Design-2.png\" alt=\"\" width=\"426\" height=\"248\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-Create-Block-Design-2.png 426w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-Create-Block-Design-2-300x175.png 300w\" sizes=\"auto, (max-width: 426px) 100vw, 426px\" \/><\/a><\/li>\n<li>Now look at the empy Block Design<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-Empty-Block-Design.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-397\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-Empty-Block-Design.png\" alt=\"\" width=\"1554\" height=\"825\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-Empty-Block-Design.png 1554w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-Empty-Block-Design-300x159.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-Empty-Block-Design-768x408.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-Empty-Block-Design-1024x544.png 1024w\" sizes=\"auto, (max-width: 1554px) 100vw, 1554px\" \/><\/a><\/li>\n<li>Click on the &#8220;Add IP&#8221; button<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-Add-Ip-To-Design.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-398\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-Add-Ip-To-Design.png\" alt=\"\" width=\"358\" height=\"151\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-Add-Ip-To-Design.png 358w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-Add-Ip-To-Design-300x127.png 300w\" sizes=\"auto, (max-width: 358px) 100vw, 358px\" \/><\/a><\/li>\n<li>Start typing in MicroBlaze, and make sure you select &#8220;MicroBlaze&#8221; and not &#8220;MicroBlaze MCS&#8221;.\u00a0 The MicroBlaze MCS is a striped down version of the MicroBlaze which is very easy to use, but hard to bring in to LabVIEW.\u00a0 Well, it is not hard to bring in to LabVIEW, I just have not figured out how to bring it in and for the UART to work!<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-Add-MicroBlaze.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-399\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-Add-MicroBlaze.png\" alt=\"\" width=\"347\" height=\"381\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-Add-MicroBlaze.png 347w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-Add-MicroBlaze-273x300.png 273w\" sizes=\"auto, (max-width: 347px) 100vw, 347px\" \/><\/a><\/li>\n<li>Look at the MicroBlaze IP.\u00a0 I hear in older version of the Xilinx Tools &#8211; namely ISE &#8211; there was no such picture, but instead you were given a list of signals and ports&#8230;<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-After-Adding-MicroBlaze.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-400\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-After-Adding-MicroBlaze.png\" alt=\"\" width=\"527\" height=\"361\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-After-Adding-MicroBlaze.png 527w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-After-Adding-MicroBlaze-300x206.png 300w\" sizes=\"auto, (max-width: 527px) 100vw, 527px\" \/><\/a><\/li>\n<li>Now click on &#8220;Run Block Automation&#8221;, this will bring up a wizard where you can set a bunch of parameters, such as how much memory should be used and what peripherals it can support<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/14-Clock-Run-Block-Automation.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-401\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/14-Clock-Run-Block-Automation.png\" alt=\"\" width=\"337\" height=\"95\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/14-Clock-Run-Block-Automation.png 337w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/14-Clock-Run-Block-Automation-300x85.png 300w\" sizes=\"auto, (max-width: 337px) 100vw, 337px\" \/><\/a><\/li>\n<li>This is what the defaults look like:<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/15-Default-Options.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-402\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/15-Default-Options.png\" alt=\"\" width=\"876\" height=\"548\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/15-Default-Options.png 876w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/15-Default-Options-300x188.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/15-Default-Options-768x480.png 768w\" sizes=\"auto, (max-width: 876px) 100vw, 876px\" \/><\/a><\/li>\n<li>I set the following parameters:\n<ul>\n<li>Local Memory: 128KB<\/li>\n<li>Cache Configuration: 64KB<\/li>\n<li>Debug Module: None (Can&#8217;t debug from LabVIEW at the moment)<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/16-With-Selections.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-403\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/16-With-Selections.png\" alt=\"\" width=\"876\" height=\"548\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/16-With-Selections.png 876w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/16-With-Selections-300x188.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/16-With-Selections-768x480.png 768w\" sizes=\"auto, (max-width: 876px) 100vw, 876px\" \/><\/a><\/li>\n<\/ul>\n<\/li>\n<li>Here is what it looks like after block automation.\u00a0 Notice the local memory block, the Processor System Reset icon and the Clocking Wizard<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-After-Block-Automation.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-404\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-After-Block-Automation.png\" alt=\"\" width=\"1127\" height=\"554\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-After-Block-Automation.png 1127w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-After-Block-Automation-300x147.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-After-Block-Automation-768x378.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-After-Block-Automation-1024x503.png 1024w\" sizes=\"auto, (max-width: 1127px) 100vw, 1127px\" \/><\/a><\/li>\n<li>I want to remove the reset from the Clocking Wizard and to convert the input clock to a single-ended clock from a differential clock.\u00a0 A differential clock just means that there are 2 clock signals and they always have to be opposites of each other.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/18-Customize-Clocking-Wizard.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-405\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/18-Customize-Clocking-Wizard.png\" alt=\"\" width=\"445\" height=\"341\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/18-Customize-Clocking-Wizard.png 445w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/18-Customize-Clocking-Wizard-300x230.png 300w\" sizes=\"auto, (max-width: 445px) 100vw, 445px\" \/><\/a><\/li>\n<li>Here I switch the clock from &#8220;Differential Clock&#8221; to &#8220;Single-Ended Clock<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/19-Clocking-Wizard-Single-Ended.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-406\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/19-Clocking-Wizard-Single-Ended.png\" alt=\"\" width=\"1212\" height=\"822\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/19-Clocking-Wizard-Single-Ended.png 1212w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/19-Clocking-Wizard-Single-Ended-300x203.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/19-Clocking-Wizard-Single-Ended-768x521.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/19-Clocking-Wizard-Single-Ended-1024x694.png 1024w\" sizes=\"auto, (max-width: 1212px) 100vw, 1212px\" \/><\/a><a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/20-Clocking-Wizard-Single-Ended.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-407\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/20-Clocking-Wizard-Single-Ended.png\" alt=\"\" width=\"240\" height=\"202\" \/><\/a><\/li>\n<li>Here I get rid of the Reset signal, notice how the Reset Type gets grayed out automatically.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/21-Clocking-Wizard-Remove-Reset.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-408\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/21-Clocking-Wizard-Remove-Reset.png\" alt=\"\" width=\"1212\" height=\"822\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/21-Clocking-Wizard-Remove-Reset.png 1212w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/21-Clocking-Wizard-Remove-Reset-300x203.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/21-Clocking-Wizard-Remove-Reset-768x521.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/21-Clocking-Wizard-Remove-Reset-1024x694.png 1024w\" sizes=\"auto, (max-width: 1212px) 100vw, 1212px\" \/><\/a><\/li>\n<li>Now I add the &#8220;AXI Uartlite&#8221; IP.\u00a0 There is another UART IP that is available, but I have arbitrarily chosen to learn by using this one.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/22-Add-Uartlite.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-409\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/22-Add-Uartlite.png\" alt=\"\" width=\"341\" height=\"187\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/22-Add-Uartlite.png 341w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/22-Add-Uartlite-300x165.png 300w\" sizes=\"auto, (max-width: 341px) 100vw, 341px\" \/><\/a><\/li>\n<li>Now I want to customize the Uartlite IP, so just as before with the Clocking Wizard, I right-click (away from any terminals) and select &#8220;Customize Block&#8221;.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/23-Customize-Uartlite.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-410\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/23-Customize-Uartlite.png\" alt=\"\" width=\"456\" height=\"353\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/23-Customize-Uartlite.png 456w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/23-Customize-Uartlite-300x232.png 300w\" sizes=\"auto, (max-width: 456px) 100vw, 456px\" \/><\/a><\/li>\n<li>I set the Baud Rate to 128,000, I leave the number of data bits to 8, and I set even parity.\u00a0 Note that I chose to add a parity because I want my UART connection to be more exact and to receive less (if no) garbled text.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/24-Uartlite-Settings.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-411\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/24-Uartlite-Settings.png\" alt=\"\" width=\"728\" height=\"433\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/24-Uartlite-Settings.png 728w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/24-Uartlite-Settings-300x178.png 300w\" sizes=\"auto, (max-width: 728px) 100vw, 728px\" \/><\/a><\/li>\n<li>Now for the fun part&#8230; Click on &#8220;Run Connection Automation&#8221; and watch as Vivado wires up all of our IP and components together!<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/25-Connection-Automation.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-412\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/25-Connection-Automation.png\" alt=\"\" width=\"416\" height=\"70\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/25-Connection-Automation.png 416w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/25-Connection-Automation-300x50.png 300w\" sizes=\"auto, (max-width: 416px) 100vw, 416px\" \/><\/a><\/li>\n<li>All of the default options are fine, but I have included screen shots so that you can see all the details yourself:<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/26-Defaults-Are-Okay.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-413\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/26-Defaults-Are-Okay.png\" alt=\"\" width=\"876\" height=\"548\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/26-Defaults-Are-Okay.png 876w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/26-Defaults-Are-Okay-300x188.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/26-Defaults-Are-Okay-768x480.png 768w\" sizes=\"auto, (max-width: 876px) 100vw, 876px\" \/><\/a><a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/27-Uartlite-Connection.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-414\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/27-Uartlite-Connection.png\" alt=\"\" width=\"876\" height=\"548\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/27-Uartlite-Connection.png 876w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/27-Uartlite-Connection-300x188.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/27-Uartlite-Connection-768x480.png 768w\" sizes=\"auto, (max-width: 876px) 100vw, 876px\" \/><\/a><a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/28-Reset-Wizard.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-415\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/28-Reset-Wizard.png\" alt=\"\" width=\"876\" height=\"548\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/28-Reset-Wizard.png 876w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/28-Reset-Wizard-300x188.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/28-Reset-Wizard-768x480.png 768w\" sizes=\"auto, (max-width: 876px) 100vw, 876px\" \/><\/a><\/li>\n<li>Now after this completes, the block design will look pretty messy, so click on the &#8220;Refresh&#8221; looking icon below to regenerate the layout:<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/29-Clean-up-View.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-416\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/29-Clean-up-View.png\" alt=\"\" width=\"81\" height=\"247\" \/><\/a><\/li>\n<li>Here is a cleaned up version of the Block Design.\u00a0 Notice that the &#8220;Run Block Automation&#8221; option is still there.\u00a0 Nothing has gone wrong, this text is there because we now have to wire up the Data and Instruction Caches.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/30-Full-View.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-417\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/30-Full-View.png\" alt=\"\" width=\"1667\" height=\"899\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/30-Full-View.png 1667w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/30-Full-View-300x162.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/30-Full-View-768x414.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/30-Full-View-1024x552.png 1024w\" sizes=\"auto, (max-width: 1667px) 100vw, 1667px\" \/><\/a><\/li>\n<li>Again, the default options are fine<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/31-Run-Connection-Automation-Caches.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-418\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/31-Run-Connection-Automation-Caches.png\" alt=\"\" width=\"876\" height=\"548\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/31-Run-Connection-Automation-Caches.png 876w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/31-Run-Connection-Automation-Caches-300x188.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/31-Run-Connection-Automation-Caches-768x480.png 768w\" sizes=\"auto, (max-width: 876px) 100vw, 876px\" \/><\/a><\/li>\n<li>And finally&#8230; our block design is ready.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/32-Final-View.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-419\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/32-Final-View.png\" alt=\"\" width=\"1858\" height=\"1103\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/32-Final-View.png 1858w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/32-Final-View-300x178.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/32-Final-View-768x456.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/32-Final-View-1024x608.png 1024w\" sizes=\"auto, (max-width: 1858px) 100vw, 1858px\" \/><\/a><\/li>\n<li>Now we will generate an HDL Wrapper file.\u00a0 This is not required for the Block Design, but it will help us with the importing of this design in to LabVIEW later.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/33-Create-HDL-Wrapper.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-420\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/33-Create-HDL-Wrapper.png\" alt=\"\" width=\"497\" height=\"489\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/33-Create-HDL-Wrapper.png 497w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/33-Create-HDL-Wrapper-300x295.png 300w\" sizes=\"auto, (max-width: 497px) 100vw, 497px\" \/><\/a><\/li>\n<li>Now we will click on &#8220;Export-&gt;Export Block Design&#8221;, this will generate a tcl script that we can run or &#8220;source&#8221; from another Vivado project and this block design will be regenerated for us.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/34-Export-Block-Design.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-421\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/34-Export-Block-Design.png\" alt=\"\" width=\"471\" height=\"184\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/34-Export-Block-Design.png 471w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/34-Export-Block-Design-300x117.png 300w\" sizes=\"auto, (max-width: 471px) 100vw, 471px\" \/><\/a><a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/35-Export-Block-Design-Options.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-422\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/35-Export-Block-Design-Options.png\" alt=\"\" width=\"526\" height=\"198\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/35-Export-Block-Design-Options.png 526w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/35-Export-Block-Design-Options-300x113.png 300w\" sizes=\"auto, (max-width: 526px) 100vw, 526px\" \/><\/a><\/li>\n<li>Note the location of the wrapper VHDL.\u00a0 Copy this file to your clipboard<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/36-Copy-Wrapper-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-423\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/36-Copy-Wrapper-1.png\" alt=\"\" width=\"1233\" height=\"711\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/36-Copy-Wrapper-1.png 1233w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/36-Copy-Wrapper-1-300x173.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/36-Copy-Wrapper-1-768x443.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/36-Copy-Wrapper-1-1024x590.png 1024w\" sizes=\"auto, (max-width: 1233px) 100vw, 1233px\" \/><\/a><\/li>\n<li>Place it in to the root directory of your project, a location that you will commit to source control.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/37-Copy-Wrapper-2.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-424\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/37-Copy-Wrapper-2.png\" alt=\"\" width=\"1233\" height=\"711\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/37-Copy-Wrapper-2.png 1233w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/37-Copy-Wrapper-2-300x173.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/37-Copy-Wrapper-2-768x443.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/37-Copy-Wrapper-2-1024x590.png 1024w\" sizes=\"auto, (max-width: 1233px) 100vw, 1233px\" \/><\/a><\/li>\n<li>The Tcl file should also be in the same directory<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/38-Remove-Original-Project.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-425\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/38-Remove-Original-Project.png\" alt=\"\" width=\"1233\" height=\"711\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/38-Remove-Original-Project.png 1233w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/38-Remove-Original-Project-300x173.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/38-Remove-Original-Project-768x443.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/38-Remove-Original-Project-1024x590.png 1024w\" sizes=\"auto, (max-width: 1233px) 100vw, 1233px\" \/><\/a><\/li>\n<\/ul>\n<h1>Part 2 &#8211; (Optional) How to Recreate MicroBlaze Design from Source TCL Script<\/h1>\n<p>So Vivado is not like other programming languages where you create your gitignore file and commit the rest to source code control.\u00a0 In Vivado, you generate a TCL script that will re-generate your entire project &#8211; or in our case &#8211; a specific Block Design.\u00a0 This script will also import any other files such as VHDL files or constraints files that are required.\u00a0 In our case we have a very simple design that does not require any such helper files.<\/p>\n<ul class=\"ili-indent\">\n<li>Click on Create New Project:\n<ul>\n<li><a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/01-Create-New-Project-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-436\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/01-Create-New-Project-1.png\" alt=\"\" width=\"148\" height=\"126\" \/><\/a><\/li>\n<\/ul>\n<\/li>\n<li>Same as before, first couple of steps just click &#8220;Next&#8221;<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-New-Project-Wizard-1-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-438\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-New-Project-Wizard-1-1.png\" alt=\"\" width=\"743\" height=\"528\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-New-Project-Wizard-1-1.png 743w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-New-Project-Wizard-1-1-300x213.png 300w\" sizes=\"auto, (max-width: 743px) 100vw, 743px\" \/><\/a><\/li>\n<li>This time I will call the project &#8220;mb_uart.imp&#8221;, to differentiate it from the project that I created.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-New-Project-Wizard-2-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-439\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-New-Project-Wizard-2-1.png\" alt=\"\" width=\"743\" height=\"528\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-New-Project-Wizard-2-1.png 743w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-New-Project-Wizard-2-1-300x213.png 300w\" sizes=\"auto, (max-width: 743px) 100vw, 743px\" \/><\/a><\/li>\n<li>Again, RTL project, and do not specify any sources at this time<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/04-New-Project-Wizard-3-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-440\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/04-New-Project-Wizard-3-1.png\" alt=\"\" width=\"743\" height=\"528\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/04-New-Project-Wizard-3-1.png 743w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/04-New-Project-Wizard-3-1-300x213.png 300w\" sizes=\"auto, (max-width: 743px) 100vw, 743px\" \/><\/a><\/li>\n<li>Same part as before.\u00a0 Not sure if you can import a block design to other FPGAs, perhaps if they have the same family or series, but I have not tried this out yet.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-New-Project-Wizard-4-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-441\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-New-Project-Wizard-4-1.png\" alt=\"\" width=\"743\" height=\"528\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-New-Project-Wizard-4-1.png 743w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-New-Project-Wizard-4-1-300x213.png 300w\" sizes=\"auto, (max-width: 743px) 100vw, 743px\" \/><\/a><\/li>\n<li>Project Summary<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/06-New-Project-Wizard-5-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-442\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/06-New-Project-Wizard-5-1.png\" alt=\"\" width=\"743\" height=\"528\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/06-New-Project-Wizard-5-1.png 743w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/06-New-Project-Wizard-5-1-300x213.png 300w\" sizes=\"auto, (max-width: 743px) 100vw, 743px\" \/><\/a><\/li>\n<li>Click on &#8220;Tcl Console&#8221;<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-Go-to-Tcl-Console-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-443\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-Go-to-Tcl-Console-1.png\" alt=\"\" width=\"390\" height=\"335\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-Go-to-Tcl-Console-1.png 390w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-Go-to-Tcl-Console-1-300x258.png 300w\" sizes=\"auto, (max-width: 390px) 100vw, 390px\" \/><\/a><\/li>\n<li>Change to the directory where the Tcl export script is located<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-Change-Directory-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-444\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-Change-Directory-1.png\" alt=\"\" width=\"407\" height=\"97\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-Change-Directory-1.png 407w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-Change-Directory-1-300x71.png 300w\" sizes=\"auto, (max-width: 407px) 100vw, 407px\" \/><\/a><\/li>\n<li>Type dir if you like.\u00a0 Notice how &#8220;known Tcl&#8221; commands are sent to the underlying os for execution<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-Dir-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-445\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-Dir-1.png\" alt=\"\" width=\"814\" height=\"351\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-Dir-1.png 814w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-Dir-1-300x129.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-Dir-1-768x331.png 768w\" sizes=\"auto, (max-width: 814px) 100vw, 814px\" \/><\/a><\/li>\n<li>And finally, &#8220;source&#8221; the tcl script<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-Source-Tcl-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-446\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-Source-Tcl-1.png\" alt=\"\" width=\"580\" height=\"124\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-Source-Tcl-1.png 580w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-Source-Tcl-1-300x64.png 300w\" sizes=\"auto, (max-width: 580px) 100vw, 580px\" \/><\/a><\/li>\n<li>And here is the imported Block Design<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-Design-Recreated-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-447\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-Design-Recreated-1.png\" alt=\"\" width=\"1858\" height=\"1103\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-Design-Recreated-1.png 1858w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-Design-Recreated-1-300x178.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-Design-Recreated-1-768x456.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-Design-Recreated-1-1024x608.png 1024w\" sizes=\"auto, (max-width: 1858px) 100vw, 1858px\" \/><\/a><\/li>\n<li>And that&#8217;s it! Create an HDL Wrapper if you like<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-Recreate-HDL-Wrapper-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-448\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-Recreate-HDL-Wrapper-1.png\" alt=\"\" width=\"532\" height=\"322\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-Recreate-HDL-Wrapper-1.png 532w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-Recreate-HDL-Wrapper-1-300x182.png 300w\" sizes=\"auto, (max-width: 532px) 100vw, 532px\" \/><\/a><\/li>\n<\/ul>\n<h1>Part 3 &#8211; Bring Design in to LabVIEW FPGA<\/h1>\n<p>Now we have to create a CLIP (Component Level IP) Node in LabVIEW FPGA that will import this MicroBlaze Block Design.\u00a0 A CLIP node contains a top-level vhdl wrapper that usually instantiates the IP that we want to bring in to LabVIEW FPGA, but in this case I am creating a CLIP node that contains an empty wrapper for the MicroBlaze Block Design.<\/p>\n<ul class=\"ili-indent\">\n<li>Launch LabVIEW 2017 (32-bit) from the start menu\n<ul>\n<li><a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/01-Start-LabVIEW-32-bit.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-450\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/01-Start-LabVIEW-32-bit.png\" alt=\"\" width=\"263\" height=\"106\" \/><\/a><\/li>\n<\/ul>\n<\/li>\n<li>Here is the screen that appears after you start LabVIEW<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-LabVIEW-2017-Started.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-451\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-LabVIEW-2017-Started.png\" alt=\"\" width=\"800\" height=\"543\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-LabVIEW-2017-Started.png 800w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-LabVIEW-2017-Started-300x204.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-LabVIEW-2017-Started-768x521.png 768w\" sizes=\"auto, (max-width: 800px) 100vw, 800px\" \/><\/a><\/li>\n<li>Click on &#8220;Create Project&#8221;, Blank Project should be fine.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-Create-Blank-Project.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-452\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-Create-Blank-Project.png\" alt=\"\" width=\"816\" height=\"638\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-Create-Blank-Project.png 816w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-Create-Blank-Project-300x235.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-Create-Blank-Project-768x600.png 768w\" sizes=\"auto, (max-width: 816px) 100vw, 816px\" \/><\/a><\/li>\n<li>Right-click on the &#8220;My Computer&#8221; icon and select &#8220;New-&gt;Targets and Devices&#8230;&#8221;<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-Add-Fpga-Target.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-454\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-Add-Fpga-Target.png\" alt=\"\" width=\"502\" height=\"401\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-Add-Fpga-Target.png 502w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-Add-Fpga-Target-300x240.png 300w\" sizes=\"auto, (max-width: 502px) 100vw, 502px\" \/><\/a><\/li>\n<li>Select &#8220;New target or device&#8221; and select the PXIe-6592R FPGA board<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/06-Add-PXIe-6592.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-455\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/06-Add-PXIe-6592.png\" alt=\"\" width=\"459\" height=\"507\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/06-Add-PXIe-6592.png 459w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/06-Add-PXIe-6592-272x300.png 272w\" sizes=\"auto, (max-width: 459px) 100vw, 459px\" \/><\/a><\/li>\n<li>Here is what the project looks like after adding the FPGA device\/target:<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-After-Adding-PXIe-6592.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-456\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-After-Adding-PXIe-6592.png\" alt=\"\" width=\"392\" height=\"575\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-After-Adding-PXIe-6592.png 392w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-After-Adding-PXIe-6592-205x300.png 205w\" sizes=\"auto, (max-width: 392px) 100vw, 392px\" \/><\/a><\/li>\n<li>Create a FIFO for communicating from the Host to the FPGA Target, aka &#8220;Host to Target &#8211; DMA&#8221; by clicking New-&gt;FIFO:<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-Create-TX-FIFO.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-457\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-Create-TX-FIFO.png\" alt=\"\" width=\"521\" height=\"429\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-Create-TX-FIFO.png 521w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-Create-TX-FIFO-300x247.png 300w\" sizes=\"auto, (max-width: 521px) 100vw, 521px\" \/><\/a><\/li>\n<li>I follow a naming standard that ALE System Integration follows which is to prepend &#8220;HT&#8221; or &#8220;TH&#8221; to the name of each FIFO, where HT stands for Host to Target, and TH stands for Target to Host, so I name this FIFO &#8220;HT-UART_TX&#8221;:<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-TX-FIFO-Options-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-458\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-TX-FIFO-Options-1.png\" alt=\"\" width=\"827\" height=\"584\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-TX-FIFO-Options-1.png 827w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-TX-FIFO-Options-1-300x212.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-TX-FIFO-Options-1-768x542.png 768w\" sizes=\"auto, (max-width: 827px) 100vw, 827px\" \/><\/a><\/li>\n<li>I also set the Data Type of this FIFO to U8, because it will be used to receive characters<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-TX-FIFO-Options-2.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-459\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-TX-FIFO-Options-2.png\" alt=\"\" width=\"827\" height=\"584\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-TX-FIFO-Options-2.png 827w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-TX-FIFO-Options-2-300x212.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-TX-FIFO-Options-2-768x542.png 768w\" sizes=\"auto, (max-width: 827px) 100vw, 827px\" \/><\/a><\/li>\n<li>The same thing for the Receive FIFO, &#8220;TH&#8221; for Target to Host, and RX for Receive.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-RX-FIFO-Options-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-460\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-RX-FIFO-Options-1.png\" alt=\"\" width=\"827\" height=\"584\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-RX-FIFO-Options-1.png 827w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-RX-FIFO-Options-1-300x212.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-RX-FIFO-Options-1-768x542.png 768w\" sizes=\"auto, (max-width: 827px) 100vw, 827px\" \/><\/a><\/li>\n<li>Data type, again is U8.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-RX-FIFO-Options-2.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-461\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-RX-FIFO-Options-2.png\" alt=\"\" width=\"827\" height=\"584\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-RX-FIFO-Options-2.png 827w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-RX-FIFO-Options-2-300x212.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-RX-FIFO-Options-2-768x542.png 768w\" sizes=\"auto, (max-width: 827px) 100vw, 827px\" \/><\/a><\/li>\n<li>Now do you remember where the microblaze wrapper vhdl was located? Find it and copy it to the root of the LabVIEW project<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-Copy-VHDL-to-LabVIEW.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-462\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-Copy-VHDL-to-LabVIEW.png\" alt=\"\" width=\"637\" height=\"504\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-Copy-VHDL-to-LabVIEW.png 637w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-Copy-VHDL-to-LabVIEW-300x237.png 300w\" sizes=\"auto, (max-width: 637px) 100vw, 637px\" \/><\/a><\/li>\n<li>The LabVIEW project is located in the MicroBlaze_UART\/labview_fpga_uart directory:<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/14-Paste.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-463\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/14-Paste.png\" alt=\"\" width=\"561\" height=\"594\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/14-Paste.png 561w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/14-Paste-283x300.png 283w\" sizes=\"auto, (max-width: 561px) 100vw, 561px\" \/><\/a><\/li>\n<li>Rename the file by prepending &#8220;UserRTL_&#8221; to the name of the file.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/15-Rename-File.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-464\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/15-Rename-File.png\" alt=\"\" width=\"560\" height=\"252\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/15-Rename-File.png 560w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/15-Rename-File-300x135.png 300w\" sizes=\"auto, (max-width: 560px) 100vw, 560px\" \/><\/a><\/li>\n<li>Edit the file, here is what it looks like before: (Sorry for the screen shot, I will provide source code links soon):<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/16-Edit-File-Before.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-465\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/16-Edit-File-Before.png\" alt=\"\" width=\"673\" height=\"1000\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/16-Edit-File-Before.png 673w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/16-Edit-File-Before-202x300.png 202w\" sizes=\"auto, (max-width: 673px) 100vw, 673px\" \/><\/a><\/li>\n<li>Change the name of the entity to match the file right now<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-Rename-and-Empty.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-466\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-Rename-and-Empty.png\" alt=\"\" width=\"673\" height=\"776\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-Rename-and-Empty.png 673w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-Rename-and-Empty-260x300.png 260w\" sizes=\"auto, (max-width: 673px) 100vw, 673px\" \/><\/a><\/li>\n<li>Now we will create a CLIP, right-click on the FPGA target and select &#8220;Properties&#8221;<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/19-Create-CLIP-2.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-468\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/19-Create-CLIP-2.png\" alt=\"\" width=\"827\" height=\"584\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/19-Create-CLIP-2.png 827w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/19-Create-CLIP-2-300x212.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/19-Create-CLIP-2-768x542.png 768w\" sizes=\"auto, (max-width: 827px) 100vw, 827px\" \/><\/a><\/li>\n<li>Add the VHDL file that we edited before &#8211; &#8220;UserRTL_d_microblaze_wrapper.vhd&#8221;<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/20-Create-CLIP-3.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-469\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/20-Create-CLIP-3.png\" alt=\"\" width=\"838\" height=\"614\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/20-Create-CLIP-3.png 838w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/20-Create-CLIP-3-300x220.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/20-Create-CLIP-3-768x563.png 768w\" sizes=\"auto, (max-width: 838px) 100vw, 838px\" \/><\/a> <a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/21-Create-CLIP-4-Add-VHD.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-470\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/21-Create-CLIP-4-Add-VHD.png\" alt=\"\" width=\"720\" height=\"480\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/21-Create-CLIP-4-Add-VHD.png 720w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/21-Create-CLIP-4-Add-VHD-300x200.png 300w\" sizes=\"auto, (max-width: 720px) 100vw, 720px\" \/><\/a> <a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/22-Create-CLIP-5-After-Adding-VHD.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-471\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/22-Create-CLIP-5-After-Adding-VHD.png\" alt=\"\" width=\"838\" height=\"614\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/22-Create-CLIP-5-After-Adding-VHD.png 838w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/22-Create-CLIP-5-After-Adding-VHD-300x220.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/22-Create-CLIP-5-After-Adding-VHD-768x563.png 768w\" sizes=\"auto, (max-width: 838px) 100vw, 838px\" \/><\/a><\/li>\n<li>Then click Next to go to step 2 of 8.\u00a0 Here select the &#8220;Limited to families selected below&#8221; option:<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/23-Create-CLIP-6-Step-2.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-472\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/23-Create-CLIP-6-Step-2.png\" alt=\"\" width=\"838\" height=\"614\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/23-Create-CLIP-6-Step-2.png 838w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/23-Create-CLIP-6-Step-2-300x220.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/23-Create-CLIP-6-Step-2-768x563.png 768w\" sizes=\"auto, (max-width: 838px) 100vw, 838px\" \/><\/a><\/li>\n<li>Then click next to go to step 3, here you have to click on &#8220;Check Syntax&#8221; and a Xilinx application is run to check the syntax<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/24-Create-CLIP-7-Step-3-Syntax-Check.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-473\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/24-Create-CLIP-7-Step-3-Syntax-Check.png\" alt=\"\" width=\"838\" height=\"614\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/24-Create-CLIP-7-Step-3-Syntax-Check.png 838w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/24-Create-CLIP-7-Step-3-Syntax-Check-300x220.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/24-Create-CLIP-7-Step-3-Syntax-Check-768x563.png 768w\" sizes=\"auto, (max-width: 838px) 100vw, 838px\" \/><\/a><\/li>\n<li>Now for step 4, click on the &#8220;clock_rtl&#8221; signal and make sure it is set to &#8220;Signal type&#8221; of clock.\u00a0 Don&#8217;t worry about the reset signal, we want to control this ourselves.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/25-Create-CLIP-8-Step-4-Clock.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-474\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/25-Create-CLIP-8-Step-4-Clock.png\" alt=\"\" width=\"838\" height=\"614\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/25-Create-CLIP-8-Step-4-Clock.png 838w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/25-Create-CLIP-8-Step-4-Clock-300x220.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/25-Create-CLIP-8-Step-4-Clock-768x563.png 768w\" sizes=\"auto, (max-width: 838px) 100vw, 838px\" \/><\/a><\/li>\n<li>For step 5, nothing is required, so skip and go to step 6<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/26-Create-CLIP-9-Step-5.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-475\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/26-Create-CLIP-9-Step-5.png\" alt=\"\" width=\"838\" height=\"614\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/26-Create-CLIP-9-Step-5.png 838w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/26-Create-CLIP-9-Step-5-300x220.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/26-Create-CLIP-9-Step-5-768x563.png 768w\" sizes=\"auto, (max-width: 838px) 100vw, 838px\" \/><\/a><\/li>\n<li>Same thing for Step 6, just click next<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/27-Create-CLIP-10-Step-6.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-476\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/27-Create-CLIP-10-Step-6.png\" alt=\"\" width=\"838\" height=\"614\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/27-Create-CLIP-10-Step-6.png 838w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/27-Create-CLIP-10-Step-6-300x220.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/27-Create-CLIP-10-Step-6-768x563.png 768w\" sizes=\"auto, (max-width: 838px) 100vw, 838px\" \/><\/a><\/li>\n<li>For step 7, just make sure that all signals are &#8220;Allowed&#8221; inside a Single-Cycle Timed Loop.\u00a0 You can probably also required this, but we will not be doing that today.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/28-Create-CLIP-11-Step-7.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-477\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/28-Create-CLIP-11-Step-7.png\" alt=\"\" width=\"838\" height=\"614\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/28-Create-CLIP-11-Step-7.png 838w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/28-Create-CLIP-11-Step-7-300x220.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/28-Create-CLIP-11-Step-7-768x563.png 768w\" sizes=\"auto, (max-width: 838px) 100vw, 838px\" \/><\/a><\/li>\n<li>Step 8 &#8211; Click Finish.\u00a0<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/29-Create-CLIP-12-Step-8.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-478\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/29-Create-CLIP-12-Step-8.png\" alt=\"\" width=\"838\" height=\"614\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/29-Create-CLIP-12-Step-8.png 838w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/29-Create-CLIP-12-Step-8-300x220.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/29-Create-CLIP-12-Step-8-768x563.png 768w\" sizes=\"auto, (max-width: 838px) 100vw, 838px\" \/><\/a><\/li>\n<li>We are finished, now a CLIP is available for us to use in our FPGA design, but it has not been instantiated.\u00a0 I believe you can have multiple instances of the same CLIP.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/30-After-Creating-CLIP.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-479\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/30-After-Creating-CLIP.png\" alt=\"\" width=\"827\" height=\"584\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/30-After-Creating-CLIP.png 827w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/30-After-Creating-CLIP-300x212.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/30-After-Creating-CLIP-768x542.png 768w\" sizes=\"auto, (max-width: 827px) 100vw, 827px\" \/><\/a><\/li>\n<li>Before we go any further, we have to add a clock for the MicroBlaze.\u00a0 Our design will be 100 MHz, so right-clock on the 40 MHz clock and click on &#8220;New FPGA Derived Clock&#8221;<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/31-Create-100MHz-Clock.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-480\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/31-Create-100MHz-Clock.png\" alt=\"\" width=\"373\" height=\"201\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/31-Create-100MHz-Clock.png 373w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/31-Create-100MHz-Clock-300x162.png 300w\" sizes=\"auto, (max-width: 373px) 100vw, 373px\" \/><\/a><\/li>\n<li>Type 100 in to the &#8220;Desired Derived Frequency&#8221; box, and everything else should automatically update.\u00a0 Then click OK<img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-482\" style=\"font-size: 1rem;\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/32-Create-100MHz-Clock-2.png\" alt=\"\" width=\"827\" height=\"584\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/32-Create-100MHz-Clock-2.png 827w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/32-Create-100MHz-Clock-2-300x212.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/32-Create-100MHz-Clock-2-768x542.png 768w\" sizes=\"auto, (max-width: 827px) 100vw, 827px\" \/><\/li>\n<li>Now we also have to set our top-level clock to be 100MHz.\u00a0 So right-click on the FPGA Target and select properties, and in the following dialog select &#8220;Top-Level Clock&#8221; and select the new clock.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/32a-Set-100MHz-Top-Level.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-481\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/32a-Set-100MHz-Top-Level.png\" alt=\"\" width=\"827\" height=\"584\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/32a-Set-100MHz-Top-Level.png 827w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/32a-Set-100MHz-Top-Level-300x212.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/32a-Set-100MHz-Top-Level-768x542.png 768w\" sizes=\"auto, (max-width: 827px) 100vw, 827px\" \/><\/a><\/li>\n<li>Now we will add an instance of the CLIP.\u00a0 Right-click on the FPGA Target and select &#8220;New-&gt;Component-Level IP<img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-483\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/33-Add-CLIP-Instance.png\" alt=\"\" width=\"612\" height=\"487\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/33-Add-CLIP-Instance.png 612w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/33-Add-CLIP-Instance-300x239.png 300w\" sizes=\"auto, (max-width: 612px) 100vw, 612px\" \/><\/li>\n<li>Select the UserRTL_d_microblaze_wrapper<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/34-Add-CLIP-Instance-2.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-484\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/34-Add-CLIP-Instance-2.png\" alt=\"\" width=\"854\" height=\"624\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/34-Add-CLIP-Instance-2.png 854w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/34-Add-CLIP-Instance-2-300x219.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/34-Add-CLIP-Instance-2-768x561.png 768w\" sizes=\"auto, (max-width: 854px) 100vw, 854px\" \/><\/a><a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/35-Add-CLIP-Instance-3.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-485\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/35-Add-CLIP-Instance-3.png\" alt=\"\" width=\"827\" height=\"584\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/35-Add-CLIP-Instance-3.png 827w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/35-Add-CLIP-Instance-3-300x212.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/35-Add-CLIP-Instance-3-768x542.png 768w\" sizes=\"auto, (max-width: 827px) 100vw, 827px\" \/><\/a><\/li>\n<li>And on the &#8220;Clock Selection&#8221; page, select the 100MHz clock.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/36-Add-CLIP-Instance-4-Select-Clock.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-486\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/36-Add-CLIP-Instance-4-Select-Clock.png\" alt=\"\" width=\"827\" height=\"584\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/36-Add-CLIP-Instance-4-Select-Clock.png 827w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/36-Add-CLIP-Instance-4-Select-Clock-300x212.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/36-Add-CLIP-Instance-4-Select-Clock-768x542.png 768w\" sizes=\"auto, (max-width: 827px) 100vw, 827px\" \/><\/a><\/li>\n<li>Now we will add some existing vi&#8217;s<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/37-Save-Time-FPGA-Import-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-487\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/37-Save-Time-FPGA-Import-1.png\" alt=\"\" width=\"540\" height=\"337\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/37-Save-Time-FPGA-Import-1.png 540w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/37-Save-Time-FPGA-Import-1-300x187.png 300w\" sizes=\"auto, (max-width: 540px) 100vw, 540px\" \/><\/a><\/li>\n<li>And here is what our final project looks like:<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/39-After-FPGA-Import.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-489\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/39-After-FPGA-Import.png\" alt=\"\" width=\"392\" height=\"575\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/39-After-FPGA-Import.png 392w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/39-After-FPGA-Import-205x300.png 205w\" sizes=\"auto, (max-width: 392px) 100vw, 392px\" \/><\/a><\/li>\n<\/ul>\n<h1>Part 4 &#8211; Create LabVIEW Host Wrapper<\/h1>\n<p>LabVIEW Host applications run as native Windows processes<\/p>\n<ul class=\"ili-indent\">\n<li>Now we will add the Host LabVIEW application vis.\u00a0 A LabVIEW Host application is a native Windows executable and thanks to a bunch of libraries written by National Instruments will handle all of our communications with the FPGA.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/01-Save-Time-Import.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-490\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/01-Save-Time-Import.png\" alt=\"\" width=\"536\" height=\"286\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/01-Save-Time-Import.png 536w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/01-Save-Time-Import-300x160.png 300w\" sizes=\"auto, (max-width: 536px) 100vw, 536px\" \/><\/a><\/li>\n<li>Add the existing files<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-Save-Time-Import-2.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-491\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-Save-Time-Import-2.png\" alt=\"\" width=\"720\" height=\"480\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-Save-Time-Import-2.png 720w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-Save-Time-Import-2-300x200.png 300w\" sizes=\"auto, (max-width: 720px) 100vw, 720px\" \/><\/a><\/li>\n<li>Here is what the project looks like with all of the Host VIs.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-After-Import.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-492\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-After-Import.png\" alt=\"\" width=\"392\" height=\"575\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-After-Import.png 392w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-After-Import-205x300.png 205w\" sizes=\"auto, (max-width: 392px) 100vw, 392px\" \/><\/a><\/li>\n<\/ul>\n<h1>Part 5 &#8211; Export Project to Vivado<\/h1>\n<p>LabVIEW has introduced a new feature, the ability to export an entire FPGA design to Vivado, which allows you to import any existing IP.\u00a0 All you have to do is define one or more CLIP IPs that define the interface with your design.<\/p>\n<ul class=\"ili-indent\">\n<li>Right click on the Build Specification inside the FPGA Target and select &#8220;New-&gt;Project Export for Vivado&#8221;<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/01-Create-Build-Specification.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-493\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/01-Create-Build-Specification.png\" alt=\"\" width=\"484\" height=\"533\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/01-Create-Build-Specification.png 484w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/01-Create-Build-Specification-272x300.png 272w\" sizes=\"auto, (max-width: 484px) 100vw, 484px\" \/><\/a><\/li>\n<li>Give the build specification a name, I recommend keeping it short and sweet.\u00a0 So change it from &#8220;My Project Export for Vivado Design Suite&#8221; to something like &#8220;FpgaUart&#8221;<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-Before-Changes.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-494\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-Before-Changes.png\" alt=\"\" width=\"866\" height=\"583\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-Before-Changes.png 866w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-Before-Changes-300x202.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-Before-Changes-768x517.png 768w\" sizes=\"auto, (max-width: 866px) 100vw, 866px\" \/><\/a><\/li>\n<li>I always set &#8220;Auto increment&#8221; to true.<\/li>\n<li><a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-After-Changes-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-495\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-After-Changes-1.png\" alt=\"\" width=\"866\" height=\"583\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-After-Changes-1.png 866w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-After-Changes-1-300x202.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-After-Changes-1-768x517.png 768w\" sizes=\"auto, (max-width: 866px) 100vw, 866px\" \/><\/a><\/li>\n<li>Then on the &#8220;Source Files&#8221; tab and select the &#8220;Fpga-Uart-Exercisor.vi&#8221; to be the top level<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/04-Select-Top-Level.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-496\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/04-Select-Top-Level.png\" alt=\"\" width=\"866\" height=\"583\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/04-Select-Top-Level.png 866w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/04-Select-Top-Level-300x202.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/04-Select-Top-Level-768x517.png 768w\" sizes=\"auto, (max-width: 866px) 100vw, 866px\" \/><\/a><\/li>\n<li>Now there is a new Build Specification.\u00a0 Clock on Build<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-Build-Vivado.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-497\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-Build-Vivado.png\" alt=\"\" width=\"387\" height=\"591\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-Build-Vivado.png 387w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-Build-Vivado-196x300.png 196w\" sizes=\"auto, (max-width: 387px) 100vw, 387px\" \/><\/a><\/li>\n<li>After it completes, you can launch Vivado by clicking on the button below.\n<ul>\n<li><a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-Launch-Vivado-Design-Suite.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-498\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-Launch-Vivado-Design-Suite.png\" alt=\"\" width=\"400\" height=\"216\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-Launch-Vivado-Design-Suite.png 400w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-Launch-Vivado-Design-Suite-300x162.png 300w\" sizes=\"auto, (max-width: 400px) 100vw, 400px\" \/><\/a><\/li>\n<\/ul>\n<\/li>\n<li>Here is what the Vivado project looks like.\u00a0 All of the IP files are encrypted, except for the files we added for our CLIP.\u00a0 Since we added only one file, that is all we will see.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-After-Export.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-499\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-After-Export.png\" alt=\"\" width=\"1858\" height=\"1103\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-After-Export.png 1858w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-After-Export-300x178.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-After-Export-768x456.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-After-Export-1024x608.png 1024w\" sizes=\"auto, (max-width: 1858px) 100vw, 1858px\" \/><\/a><\/li>\n<li>Now we will import our Block Design.\u00a0 Locate the &#8220;Tcl Console&#8221; in the bottom window.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-Go-To-TCL-Console.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-500\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-Go-To-TCL-Console.png\" alt=\"\" width=\"788\" height=\"306\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-Go-To-TCL-Console.png 788w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-Go-To-TCL-Console-300x116.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-Go-To-TCL-Console-768x298.png 768w\" sizes=\"auto, (max-width: 788px) 100vw, 788px\" \/><\/a><\/li>\n<li>This console supports TCL commands as well as regular operating system commands.\u00a0 Since we are on Windows, we would like to change our current working directory to be where our d_microblaze.tcl file is located.\u00a0 Remember, Vivado uses the backslash &#8216;\\&#8217; as its escape character, so you will have to enter the backslash twice for each time you would like to use it.\n<ul>\n<li><a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-Change-Dir-to-Export-Tcl.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-501\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-Change-Dir-to-Export-Tcl.png\" alt=\"\" width=\"381\" height=\"70\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-Change-Dir-to-Export-Tcl.png 381w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-Change-Dir-to-Export-Tcl-300x55.png 300w\" sizes=\"auto, (max-width: 381px) 100vw, 381px\" \/><\/a><\/li>\n<\/ul>\n<\/li>\n<li>Now we have to source our file by issuing the &#8220;source d_microblaze.tcl&#8221; command:<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-Source-Tcl-Script.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-502\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-Source-Tcl-Script.png\" alt=\"\" width=\"895\" height=\"126\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-Source-Tcl-Script.png 895w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-Source-Tcl-Script-300x42.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-Source-Tcl-Script-768x108.png 768w\" sizes=\"auto, (max-width: 895px) 100vw, 895px\" \/><\/a><\/li>\n<li>This will take a couple of seconds, depending on the speed of your computer.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-Importing.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-503\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-Importing.png\" alt=\"\" width=\"620\" height=\"110\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-Importing.png 620w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-Importing-300x53.png 300w\" sizes=\"auto, (max-width: 620px) 100vw, 620px\" \/><\/a><\/li>\n<li>After it finishes importing\/re-creating the design, this is what you should see:<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-After-BD-Import.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-504\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-After-BD-Import.png\" alt=\"\" width=\"1858\" height=\"1103\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-After-BD-Import.png 1858w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-After-BD-Import-300x178.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-After-BD-Import-768x456.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-After-BD-Import-1024x608.png 1024w\" sizes=\"auto, (max-width: 1858px) 100vw, 1858px\" \/><\/a><\/li>\n<li>Now we go back to our &#8220;UserRTL_d_microblaze_wrapper.vhd&#8221; vhdl wrapper file and remove the comments enabling the code that uses the MicroBlaze.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/14-Uncomment-BD-from-VHDL.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-505\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/14-Uncomment-BD-from-VHDL.png\" alt=\"\" width=\"1858\" height=\"1103\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/14-Uncomment-BD-from-VHDL.png 1858w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/14-Uncomment-BD-from-VHDL-300x178.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/14-Uncomment-BD-from-VHDL-768x456.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/14-Uncomment-BD-from-VHDL-1024x608.png 1024w\" sizes=\"auto, (max-width: 1858px) 100vw, 1858px\" \/><\/a><\/li>\n<li>Now you will see that this new design appears under the VHDL wrapper file\n<ul>\n<li><a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/15-After-Uncommenting-Sub-Design.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-506\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/15-After-Uncommenting-Sub-Design.png\" alt=\"\" width=\"447\" height=\"476\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/15-After-Uncommenting-Sub-Design.png 447w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/15-After-Uncommenting-Sub-Design-282x300.png 282w\" sizes=\"auto, (max-width: 447px) 100vw, 447px\" \/><\/a><\/li>\n<\/ul>\n<\/li>\n<li>Now we have to export this entire design to Xilinx SDK so we can generate an executable to run.\u00a0 Click &#8220;File-&gt;Export-&gt;Export Hardware&#8221;<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/16-Export-Hardware.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-507\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/16-Export-Hardware.png\" alt=\"\" width=\"487\" height=\"683\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/16-Export-Hardware.png 487w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/16-Export-Hardware-214x300.png 214w\" sizes=\"auto, (max-width: 487px) 100vw, 487px\" \/><\/a><\/li>\n<li>We have not run &#8220;Generate Output Products&#8221; for the MicroBlaze, so we will be prompted to do so.\u00a0 Make sure you click &#8220;Generate Output Products&#8221;.\u00a0 If you are more experienced than me in Vivado, perhaps you know if this step is required.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-Generate-Output-Products.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-508\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-Generate-Output-Products.png\" alt=\"\" width=\"527\" height=\"143\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-Generate-Output-Products.png 527w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-Generate-Output-Products-300x81.png 300w\" sizes=\"auto, (max-width: 527px) 100vw, 527px\" \/><\/a> <a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/18-After-Generate-Output-Products-Completes.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-509\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/18-After-Generate-Output-Products-Completes.png\" alt=\"\" width=\"370\" height=\"143\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/18-After-Generate-Output-Products-Completes.png 370w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/18-After-Generate-Output-Products-Completes-300x116.png 300w\" sizes=\"auto, (max-width: 370px) 100vw, 370px\" \/><\/a><\/li>\n<li>The default directory is fine.\n<ul>\n<li><a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/19-Export-Hardware.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-510\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/19-Export-Hardware.png\" alt=\"\" width=\"331\" height=\"209\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/19-Export-Hardware.png 331w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/19-Export-Hardware-300x189.png 300w\" sizes=\"auto, (max-width: 331px) 100vw, 331px\" \/><\/a><\/li>\n<\/ul>\n<\/li>\n<li>The directory will be named &#8220;FpgaUart.sdk&#8221;<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/20-Where-Hardware-Export-Went.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-511\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/20-Where-Hardware-Export-Went.png\" alt=\"\" width=\"1384\" height=\"475\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/20-Where-Hardware-Export-Went.png 1384w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/20-Where-Hardware-Export-Went-300x103.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/20-Where-Hardware-Export-Went-768x264.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/20-Where-Hardware-Export-Went-1024x351.png 1024w\" sizes=\"auto, (max-width: 1384px) 100vw, 1384px\" \/><\/a><\/li>\n<\/ul>\n<h1>Part 6 &#8211; Building a C Executable for Running on the MicroBlaze Soft-Core Processor<\/h1>\n<p>Run the executable by referencing the lvbitx file<\/p>\n<ul class=\"ili-indent\">\n<li>Now open Xilinx SDK and select the &#8220;FpgaUart.sdk&#8221; directory as the workspace<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/01-Manually-Select-SDK-Directory.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-512\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/01-Manually-Select-SDK-Directory.png\" alt=\"\" width=\"620\" height=\"281\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/01-Manually-Select-SDK-Directory.png 620w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/01-Manually-Select-SDK-Directory-300x136.png 300w\" sizes=\"auto, (max-width: 620px) 100vw, 620px\" \/><\/a><\/li>\n<li>Create a new &#8220;Hardware Platform Specification&#8221; project by clicking on &#8220;File-&gt;New-&gt;Other&#8221;<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-Create-Hardware-Platform-Spec.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-513\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-Create-Hardware-Platform-Spec.png\" alt=\"\" width=\"568\" height=\"338\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-Create-Hardware-Platform-Spec.png 568w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/02-Create-Hardware-Platform-Spec-300x179.png 300w\" sizes=\"auto, (max-width: 568px) 100vw, 568px\" \/><\/a><\/li>\n<li>Select &#8220;Xilinx-&gt;Hardware Platform Specification&#8221;<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-Platform.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-514\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-Platform.png\" alt=\"\" width=\"525\" height=\"500\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-Platform.png 525w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/03-Platform-300x286.png 300w\" sizes=\"auto, (max-width: 525px) 100vw, 525px\" \/><\/a><\/li>\n<li>Select the only file in the sdk directory, the .hdf file.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/04-Select-hdf-File.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-515\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/04-Select-hdf-File.png\" alt=\"\" width=\"960\" height=\"540\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/04-Select-hdf-File.png 960w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/04-Select-hdf-File-300x169.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/04-Select-hdf-File-768x432.png 768w\" sizes=\"auto, (max-width: 960px) 100vw, 960px\" \/><\/a><\/li>\n<li>The Project name will be automatically populated<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-After.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-516\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-After.png\" alt=\"\" width=\"843\" height=\"479\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-After.png 843w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-After-300x170.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/05-After-768x436.png 768w\" sizes=\"auto, (max-width: 843px) 100vw, 843px\" \/><\/a><\/li>\n<li>Here is what everything looks like after creating the Hardware Platform Specification<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/06-After-Platform-Specification-Project-Added.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-517\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/06-After-Platform-Specification-Project-Added.png\" alt=\"\" width=\"1024\" height=\"768\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/06-After-Platform-Specification-Project-Added.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/06-After-Platform-Specification-Project-Added-300x225.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/06-After-Platform-Specification-Project-Added-768x576.png 768w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/a><\/li>\n<li>Now create an Application Project by selecting &#8220;File-&gt;Application Project&#8221;<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-Create-App-Project.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-518\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-Create-App-Project.png\" alt=\"\" width=\"681\" height=\"200\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-Create-App-Project.png 681w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/07-Create-App-Project-300x88.png 300w\" sizes=\"auto, (max-width: 681px) 100vw, 681px\" \/><\/a><\/li>\n<li>Name the project &#8220;mb_uart_1&#8221; and click next.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-Name-Project.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-519\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-Name-Project.png\" alt=\"\" width=\"525\" height=\"665\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-Name-Project.png 525w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/08-Name-Project-237x300.png 237w\" sizes=\"auto, (max-width: 525px) 100vw, 525px\" \/><\/a><\/li>\n<li>Select &#8220;Empty Application&#8221;<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-Empty-Project.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-520\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-Empty-Project.png\" alt=\"\" width=\"525\" height=\"665\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-Empty-Project.png 525w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/09-Empty-Project-237x300.png 237w\" sizes=\"auto, (max-width: 525px) 100vw, 525px\" \/><\/a><\/li>\n<li>Now we will add a new source file<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-Add-Source.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-521\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-Add-Source.png\" alt=\"\" width=\"598\" height=\"394\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-Add-Source.png 598w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/10-Add-Source-300x198.png 300w\" sizes=\"auto, (max-width: 598px) 100vw, 598px\" \/><\/a><\/li>\n<li>We will call it main.c<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-Add-C.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-522\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-Add-C.png\" alt=\"\" width=\"537\" height=\"433\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-Add-C.png 537w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/11-Add-C-300x242.png 300w\" sizes=\"auto, (max-width: 537px) 100vw, 537px\" \/><\/a><\/li>\n<li>Here is the application with an empty main.c file.\u00a0 Note that there are errors listed in the bottom window because this cannot build without a main function!<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-After-Adding-Blank.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-523\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-After-Adding-Blank.png\" alt=\"\" width=\"1246\" height=\"882\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-After-Adding-Blank.png 1246w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-After-Adding-Blank-300x212.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-After-Adding-Blank-768x544.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/12-After-Adding-Blank-1024x725.png 1024w\" sizes=\"auto, (max-width: 1246px) 100vw, 1246px\" \/><\/a><\/li>\n<li>After I cut and paste the source code for a simple UART application, the errors go away.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-Program-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-524\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-Program-1.png\" alt=\"\" width=\"1246\" height=\"882\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-Program-1.png 1246w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-Program-1-300x212.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-Program-1-768x544.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/13-Program-1-1024x725.png 1024w\" sizes=\"auto, (max-width: 1246px) 100vw, 1246px\" \/><\/a><\/li>\n<li>Now I am creating a second project with the same name but with the number 2 instead.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/14-Create-2nd-Program.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-525\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/14-Create-2nd-Program.png\" alt=\"\" width=\"525\" height=\"665\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/14-Create-2nd-Program.png 525w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/14-Create-2nd-Program-237x300.png 237w\" sizes=\"auto, (max-width: 525px) 100vw, 525px\" \/><\/a><\/li>\n<li>I am going to use the same Board Support Package of &#8220;BSP&#8221; file as before, and I am creating another Empty Application.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/15-Blank-Project.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-526\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/15-Blank-Project.png\" alt=\"\" width=\"525\" height=\"665\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/15-Blank-Project.png 525w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/15-Blank-Project-237x300.png 237w\" sizes=\"auto, (max-width: 525px) 100vw, 525px\" \/><\/a><\/li>\n<li>I add a new main.c as before.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/16-Create-Main-c.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-527\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/16-Create-Main-c.png\" alt=\"\" width=\"537\" height=\"433\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/16-Create-Main-c.png 537w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/16-Create-Main-c-300x242.png 300w\" sizes=\"auto, (max-width: 537px) 100vw, 537px\" \/><\/a><\/li>\n<li>I paste the same source code, but this time I replace all instances of &#8220;1.0&#8221; with &#8220;2.0&#8221;<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-Add-Code-2.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-528\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-Add-Code-2.png\" alt=\"\" width=\"1246\" height=\"882\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-Add-Code-2.png 1246w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-Add-Code-2-300x212.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-Add-Code-2-768x544.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/17-Add-Code-2-1024x725.png 1024w\" sizes=\"auto, (max-width: 1246px) 100vw, 1246px\" \/><\/a><\/li>\n<li>I set the active configuration to Release for both projects.\u00a0 This isn&#8217;t really necessary for a small design such as this one, but it is a good habit to have.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/18-Set-Release-Build.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-529\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/18-Set-Release-Build.png\" alt=\"\" width=\"755\" height=\"643\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/18-Set-Release-Build.png 755w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/18-Set-Release-Build-300x255.png 300w\" sizes=\"auto, (max-width: 755px) 100vw, 755px\" \/><\/a><\/li>\n<li>Now we go back to Vivado and click &#8220;Tools-&gt;Associate ELF Files&#8230;&#8221;<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/19-Vivado-Associate-Elf.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-530\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/19-Vivado-Associate-Elf.png\" alt=\"\" width=\"426\" height=\"353\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/19-Vivado-Associate-Elf.png 426w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/19-Vivado-Associate-Elf-300x249.png 300w\" sizes=\"auto, (max-width: 426px) 100vw, 426px\" \/><\/a><\/li>\n<li>We do not have to select an elf file for simulation, but you can if you wish to create a test bench for this project.\u00a0 I have done this in the past and it takes me about 3 hours to simulate 100 milliseconds.\u00a0 With the method described on this page, it becomes much easier to just swap out the elf file and to regenerate the bitstream.<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/22-Implementation-Only-Required.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-533\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/22-Implementation-Only-Required.png\" alt=\"\" width=\"540\" height=\"396\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/22-Implementation-Only-Required.png 540w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/22-Implementation-Only-Required-300x220.png 300w\" sizes=\"auto, (max-width: 540px) 100vw, 540px\" \/><\/a><\/li>\n<li>We select the first elf file &#8211; &#8220;mb_uart_1.elf&#8221;<a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/20-Vivado-Directory.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-531\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/20-Vivado-Directory.png\" alt=\"\" width=\"1055\" height=\"431\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/20-Vivado-Directory.png 1055w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/20-Vivado-Directory-300x123.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/20-Vivado-Directory-768x314.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/20-Vivado-Directory-1024x418.png 1024w\" sizes=\"auto, (max-width: 1055px) 100vw, 1055px\" \/><\/a><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-532\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/21-Elf-Selected.png\" alt=\"\" width=\"540\" height=\"346\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/21-Elf-Selected.png 540w, https:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/21-Elf-Selected-300x192.png 300w\" sizes=\"auto, (max-width: 540px) 100vw, 540px\" \/><\/li>\n<li>And finally, we click on &#8220;Generate Bitstream&#8221;\n<ul>\n<li><a style=\"font-size: 1rem;\" href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/23-Run-Generate-Bitstream.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-534\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2018\/04\/23-Run-Generate-Bitstream.png\" alt=\"\" width=\"204\" height=\"114\" \/><\/a><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Working from scratch, I created a LabVIEW FPGA project that imports a MicroBlaze design that communicates with LabVIEW via a UART, and has the ability to change the elf file in a much shorter time frame than before. I did this by adding the MicroBlaze to the project after it had been exported to Vivado, &#8230; <a title=\"LabVIEW FPGA, MicroBlaze, and UART &#8211; Full Guide\" class=\"read-more\" href=\"https:\/\/fpganow.com\/index.php\/2018\/04\/03\/labview-fpga-microblaze-and-uart-full-guide\/\" aria-label=\"Read more about LabVIEW FPGA, MicroBlaze, and UART &#8211; Full Guide\">Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","footnotes":""},"categories":[11,7,6,8,13,14],"tags":[15,16,18,17],"class_list":["post-385","post","type-post","status-publish","format-standard","hentry","category-clip","category-fpga","category-labview","category-microblaze","category-uart","category-uartlite","tag-labview-fpga","tag-microblaze","tag-project-export-for-vivado","tag-uart","masonry-post","generate-columns","tablet-grid-50","mobile-grid-100","grid-parent","grid-50"],"_links":{"self":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/385","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/comments?post=385"}],"version-history":[{"count":15,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/385\/revisions"}],"predecessor-version":[{"id":546,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/385\/revisions\/546"}],"wp:attachment":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/media?parent=385"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/categories?post=385"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/tags?post=385"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}