So after some serious debugging, editing, and regenerating of the bitstream, I was able to send out an ARP response from the FPGA to my linux server, and for my linux server to send a UDP packet in to the MicroBlaze.\u00a0 This was all verified via UART debug statements.<\/p>\n
Now while I work on cleaning this all up, you can actually use this code in your project, but only if you have enough knowledge of LabVIEW and Xilinx.\u00a0 My job is to help bridge that gap, but for now:<\/p>\n
The source code is located in:<\/p>\n
https:\/\/github.com\/fpganow\/MicroBlaze_lwIP<\/a><\/p>\n The application that is to be compiled and to run on the MicroBlaze is called ‘mb_lwip’ and its source code is here:<\/p>\n https:\/\/github.com\/fpganow\/MicroBlaze_lwIP\/tree\/master\/xilinx_mb_lwip\/mb_lwip<\/a><\/p>\n To make it work, you will need to add a reference to the lwip directory, which is currently located:<\/p>\n https:\/\/github.com\/fpganow\/lwip\/tree\/master\/lwip<\/a><\/p>\n Note, that the ‘fpganow\/lwip’ repository is currently referenced as a sub-module of ‘fpganow\/MicroBlaze_lwIP’.\u00a0 I will move it of course… But I will first try to re-create this project and while I re-create the project I will move and clean things up.<\/p>\n Now on to the LabVIEW part.<\/p>\n https:\/\/github.com\/fpganow\/MicroBlaze_lwIP<\/a><\/p>\n You want to open the ‘Tests\/FPGANic\/FPGANic-Tester.vi’ program as your entry.\u00a0 Start the vi, wait for the FPGA bitfile to be downloaded and then click on the ‘polling’ button to start receiving debug information about incoming and outgoing packets.<\/p>\n","protected":false},"excerpt":{"rendered":" So after some serious debugging, editing, and regenerating of the bitstream, I was able to send out an ARP response from the FPGA to my linux server, and for my linux server to send a UDP packet in to the MicroBlaze.\u00a0 This was all verified via UART debug statements. Now while I work on cleaning … Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","footnotes":""},"categories":[7,6],"tags":[15,16,30],"class_list":["post-574","post","type-post","status-publish","format-standard","hentry","category-fpga","category-labview","tag-labview-fpga","tag-microblaze","tag-pxie-6592","masonry-post","generate-columns","tablet-grid-50","mobile-grid-100","grid-parent","grid-50"],"_links":{"self":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/574","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/comments?post=574"}],"version-history":[{"count":2,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/574\/revisions"}],"predecessor-version":[{"id":576,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/574\/revisions\/576"}],"wp:attachment":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/media?parent=574"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/categories?post=574"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/tags?post=574"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}