{"id":604,"date":"2019-04-11T12:04:32","date_gmt":"2019-04-11T12:04:32","guid":{"rendered":"http:\/\/fpganow.com\/?p=604"},"modified":"2019-04-11T12:04:32","modified_gmt":"2019-04-11T12:04:32","slug":"more-details-about-tcp","status":"publish","type":"post","link":"https:\/\/fpganow.com\/index.php\/2019\/04\/11\/more-details-about-tcp\/","title":{"rendered":"More Details About TCP"},"content":{"rendered":"\n<p>So first off, I have merged my code to master, see it here:<\/p>\n\n\n\n<p><a href=\"https:\/\/github.com\/fpganow\/MicroBlaze_lwIP\">https:\/\/github.com\/fpganow\/MicroBlaze_lwIP<\/a><\/p>\n\n\n\n<p>And while I work on updating the README.md file, here are 2 slides for you to look at:<\/p>\n\n\n\n<figure class=\"wp-block-image\"><img loading=\"lazy\" decoding=\"async\" width=\"800\" height=\"600\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2019\/04\/TCP.1.png\" alt=\"\" class=\"wp-image-605\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2019\/04\/TCP.1.png 800w, https:\/\/fpganow.com\/wp-content\/uploads\/2019\/04\/TCP.1-300x225.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2019\/04\/TCP.1-768x576.png 768w\" sizes=\"auto, (max-width: 800px) 100vw, 800px\" \/><\/figure>\n\n\n\n<p><\/p>\n\n\n\n<figure class=\"wp-block-image\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"555\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2019\/04\/TCP.2-1024x555.png\" alt=\"\" class=\"wp-image-606\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2019\/04\/TCP.2-1024x555.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2019\/04\/TCP.2-300x163.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2019\/04\/TCP.2-768x416.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2019\/04\/TCP.2.png 1181w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p>So, if you have the appropriate NI hardware, you can clone down this repository and run 1 TCP and 1 UDP session to your FPGA!<\/p>\n\n\n\n<p>Do you have an existing FPGA solution? If you follow the Vivado Project that is exported from LabVIEW FPGA, you can probably import your existing FPGA solution to National Instruments hardware, plug in the lwip TCP\/IP code that I have running on a MicroBlaze core and you will have a very rapidly customizable FPGA solution, now with TCP and UDP support.<\/p>\n\n\n\n<p>If you already are using a TCP\/IP core with your FPGA, why not give this a try? Importing cores is not that hard with LabVIEW, and if you have one why not give it a shot?<\/p>\n","protected":false},"excerpt":{"rendered":"<p>So first off, I have merged my code to master, see it here: https:\/\/github.com\/fpganow\/MicroBlaze_lwIP And while I work on updating the README.md file, here are 2 slides for you to look at: So, if you have the appropriate NI hardware, you can clone down this repository and run 1 TCP and 1 UDP session to &#8230; <a title=\"More Details About TCP\" class=\"read-more\" href=\"https:\/\/fpganow.com\/index.php\/2019\/04\/11\/more-details-about-tcp\/\" aria-label=\"Read more about More Details About TCP\">Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","footnotes":""},"categories":[1],"tags":[],"class_list":["post-604","post","type-post","status-publish","format-standard","hentry","category-uncategorized","masonry-post","generate-columns","tablet-grid-50","mobile-grid-100","grid-parent","grid-50"],"_links":{"self":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/604","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/comments?post=604"}],"version-history":[{"count":1,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/604\/revisions"}],"predecessor-version":[{"id":607,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/604\/revisions\/607"}],"wp:attachment":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/media?parent=604"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/categories?post=604"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/tags?post=604"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}