You will have to pick a non-National Instruments FPGA board that has an FPGA that uses Vivado<\/strong><\/span> (7 Series devices and above) and has a corresponding LabVIEW FPGA board that uses a device of the same family.\u00a0 What does same family mean? Well, a Virtex-7 chip such as the VX485T has the same family as the VX690T.<\/p>\n If you want to run LabVIEW on other hardware, you will have to pay for and upgrade to the premium version of this tool which exports to VHDL source code.\u00a0 (This does not appear to be available yet, as per the documentation they request that you email them.\u00a0 As for me? I am happy with the encrypted netlist for now, because it keeps things simpler and will allow for easier licensing.)<\/p>\n For this post, I am going to select the NetFPGA-1G-CML Kinex-7 FPGA Development Board<\/strong>, which has a Xilinx Kintex-7 XC7K325T FPGA<\/strong>.\u00a0 See:<\/p>\n https:\/\/netfpga.org\/site\/#\/systems\/2netfpga-1g-cml\/details\/<\/a><\/p>\n Retails for $1,499.00<\/strong><\/p>\n https:\/\/store.digilentinc.com\/netfpga-sume-virtex-7-fpga-development-board\/<\/a><\/p>\n Now that you have selected the Xilinx FPGA Family that you want to use, now you have to select a National Instruments board that uses the same FPGA family, which means Kintex-7.<\/p>\n This page has a list of Xilinx FPGA’s and corresponding National Instruments Boards:<\/p>\n https:\/\/www.ni.com\/en-us\/support\/documentation\/supplemental\/18\/xilinx-fpga-chips-for-national-instruments-rio-devices.html<\/a><\/p>\n I will be selecting the PXIe-7868R<\/strong> board.<\/p>\n Create a project with the PXIe-7858R board as one of its targets, and make a very simple top-level vi.\u00a0 Here is a very simple VI Snippet:<\/p>\n\n\n\n Right-click on the top-level vi and select ‘Create Build Specification’<\/p>\n\n\n\n And after you should see:<\/p>\n \u00a0<\/p>\n\n\n\n A new option is available under the right-click menu of the build specification called “Export to Netlist”<\/p>\n\n\n\n It runs the first steps that it normally does when you synthesize an FPGA project:<\/p>\n \u00a0<\/p>\n\n\n\n Be careful, the window just disappears and expects you to know where the netlist will be saved. (Hey, that’s much better than them sitting on it internally and not releasing it.\u00a0 And, this is one of those RTFM issues anyway…)<\/p>\n C:\\NIFPGA\\compilation\\ipexport-simple_FPGATarget_<random text><\/p>\n In my case, there is a Vivado Checkpoint file and a wrapper VHD file.<\/p>\n The code looks pretty cool.\u00a0 And remember the most important thing – ACTIVE HIGH<\/span>!<\/p>\n\n\n\n NiFpgaIPWrapper_pxie7868_dash_Top_dash_Level.vhd<\/strong><\/span><\/p>\n \u00a0<\/p>\n","protected":false},"excerpt":{"rendered":" Now you can run LabVIEW FPGA on the hardware of your choice with the new “LabVIEW FPGA IP Export Utility”.\u00a0 That sounds great, but what’s that got to do with me? (quoting Rambo 3) Step 1 – Pick a non-National Instruments FPGA Board You will have to pick a non-National Instruments FPGA board that has … Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","footnotes":""},"categories":[1],"tags":[],"class_list":["post-627","post","type-post","status-publish","format-standard","hentry","category-uncategorized","masonry-post","generate-columns","tablet-grid-50","mobile-grid-100","grid-parent","grid-50"],"_links":{"self":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/627","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/comments?post=627"}],"version-history":[{"count":6,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/627\/revisions"}],"predecessor-version":[{"id":687,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/627\/revisions\/687"}],"wp:attachment":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/media?parent=627"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/categories?post=627"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/tags?post=627"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}Step 2 – Pick a Corresponding National Instruments Board<\/strong><\/h2>\n
Step 3 – Create a LabVIEW Project using this board<\/strong><\/h2>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/05\/top-level-snippet.png\")
<\/figure>\n\n\n\nStep 4 – Create a Build Specification<\/strong><\/h2>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/05\/Create-Build-Specification.png\")
<\/figure>\n\n\n\n![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/05\/After-Create-Build-Specification.png\")
<\/figure>\n\n\n\nStep 5 – Create a Netlist Export<\/strong><\/h2>\n
![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/05\/Export-to-Netlist.png\")
<\/figure>\n\n\n\n![\"\"](\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/05\/Exporting-to-Netlist.png\")
<\/figure>\n\n\n\n-- VHDL wrapper for NiFpgaAG_pxie7868_dash_Top_dash_Level<\/code>-- Generated by LabVIEW FPGA IP Export Utility<\/code>--<\/code>-- Ports:<\/code>-- reset : Reset port. Minimum assertion length: 1 base clock cycles.<\/code>-- Minimum de-assertion length: 40 base clock cycles.<\/code>-- enable_in : Enable in port. Minimum re-initialization length: 7 base clock cycles.<\/code>-- enable_out : Enable out port.<\/code>-- enable_clr : Enable clear port.<\/code>-- ctrlind_00_B : Top level control \"B\", sync to Clk40, u32<\/code>-- ctrlind_01_A : Top level control \"A\", sync to Clk40, u32<\/code>-- ctrlind_02_SUM : Top level indicator \"SUM\", sync to Clk40, u32<\/code>-- Clk40 : Clock \"40 MHz Onboard Clock\", nominal frequency 40.00 MHz, base clock<\/code><\/p>\nlibrary ieee;<\/code>use ieee.std_logic_1164.all;<\/code><\/p>\nentity NiFpgaIPWrapper_pxie7868_dash_Top_dash_Level is<\/code>port (<\/code>reset : in std_logic;<\/code>enable_in : in std_logic;<\/code>enable_out : out std_logic;<\/code>enable_clr : in std_logic;<\/code>ctrlind_00_B : in std_logic_vector(31 downto 0);<\/code>ctrlind_01_A : in std_logic_vector(31 downto 0);<\/code>ctrlind_02_SUM : out std_logic_vector(31 downto 0);<\/code>Clk40 : in std_logic<\/code>);<\/code>end NiFpgaIPWrapper_pxie7868_dash_Top_dash_Level;<\/code><\/p>\narchitecture vhdl_labview of NiFpgaIPWrapper_pxie7868_dash_Top_dash_Level is<\/code><\/p>\ncomponent NiFpgaAG_pxie7868_dash_Top_dash_Level<\/code>port (<\/code>reset : in std_logic;<\/code>enable_in : in std_logic;<\/code>enable_out : out std_logic;<\/code>enable_clr : in std_logic;<\/code>ctrlind_00_B : in std_logic_vector(31 downto 0);<\/code>ctrlind_01_A : in std_logic_vector(31 downto 0);<\/code>ctrlind_02_SUM : out std_logic_vector(31 downto 0);<\/code>Clk40 : in std_logic;<\/code>tDiagramEnableOut : in std_logic<\/code>);<\/code>end component;<\/code><\/p>\nbegin<\/code>MyLabVIEWIP : NiFpgaAG_pxie7868_dash_Top_dash_Level<\/code>port map(<\/code>reset => reset,<\/code>enable_in => enable_in,<\/code>enable_out => enable_out,<\/code>enable_clr => enable_clr,<\/code>ctrlind_00_B => ctrlind_00_B,<\/code>ctrlind_01_A => ctrlind_01_A,<\/code>ctrlind_02_SUM => ctrlind_02_SUM,<\/code>Clk40 => Clk40,<\/code>tDiagramEnableOut => '1'<\/code>);<\/code><\/p>\nend vhdl_labview;<\/code><\/p>\n