{"id":715,"date":"2020-08-16T16:14:17","date_gmt":"2020-08-16T16:14:17","guid":{"rendered":"http:\/\/fpganow.com\/?p=715"},"modified":"2020-08-16T16:14:17","modified_gmt":"2020-08-16T16:14:17","slug":"zynqberry-update","status":"publish","type":"post","link":"https:\/\/fpganow.com\/index.php\/2020\/08\/16\/zynqberry-update\/","title":{"rendered":"Zynqberry Update"},"content":{"rendered":"\n<p>So I followed the Zynqberry tutorial here:<\/p>\n<p><a href=\"https:\/\/www.knitronics.com\/the-zynqberry-patch\/getting-started-with-the-zynqberry-in-vivado-2018-2\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/www.knitronics.com\/the-zynqberry-patch\/getting-started-with-the-zynqberry-in-vivado-2018-2<\/a><\/p>\n<p>And was able to get a basic Xilinx SDK application working on my Zynqberry, but with a twist&#8230; I used the NI LabVIEW IP Export tool to incorporate some LabVIEW code.\u00a0 For now a simple adder that just adds 2 8-bit unsigned integers and outputs a 16-bit unsigned integer.<\/p>\n<p>Anyway, the key takeaways are:<\/p>\n<ul>\n<li>Follow the tutorial exactly and re-read it in case you have any confusion<\/li>\n<li>Wrap up the default block design using my wrapper<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>So I followed the Zynqberry tutorial here: https:\/\/www.knitronics.com\/the-zynqberry-patch\/getting-started-with-the-zynqberry-in-vivado-2018-2 And was able to get a basic Xilinx SDK application working on my Zynqberry, but with a twist&#8230; I used the NI LabVIEW IP Export tool to incorporate some LabVIEW code.\u00a0 For now a simple adder that just adds 2 8-bit unsigned integers and outputs a 16-bit &#8230; <a title=\"Zynqberry Update\" class=\"read-more\" href=\"https:\/\/fpganow.com\/index.php\/2020\/08\/16\/zynqberry-update\/\" aria-label=\"Read more about Zynqberry Update\">Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","footnotes":""},"categories":[1],"tags":[],"class_list":["post-715","post","type-post","status-publish","format-standard","hentry","category-uncategorized","masonry-post","generate-columns","tablet-grid-50","mobile-grid-100","grid-parent","grid-50"],"_links":{"self":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/715","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/comments?post=715"}],"version-history":[{"count":2,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/715\/revisions"}],"predecessor-version":[{"id":718,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/715\/revisions\/718"}],"wp:attachment":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/media?parent=715"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/categories?post=715"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/tags?post=715"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}