{"id":868,"date":"2020-09-28T01:00:22","date_gmt":"2020-09-28T01:00:22","guid":{"rendered":"http:\/\/fpganow.com\/?p=868"},"modified":"2020-10-25T23:47:51","modified_gmt":"2020-10-25T23:47:51","slug":"zynqberry-with-breakout-board-and-labview","status":"publish","type":"post","link":"https:\/\/fpganow.com\/index.php\/2020\/09\/28\/zynqberry-with-breakout-board-and-labview\/","title":{"rendered":"Zynqberry with Breakout Board and LabVIEW"},"content":{"rendered":"\n<h3><span style=\"color: #ffffff;\"><strong>Source Code:<\/strong><\/span><\/h3>\n<p><a href=\"https:\/\/github.com\/fpganow\/Blink_LEDS\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/github.com\/fpganow\/Blink_LEDS<\/a><\/p>\n\n\n\n<h3>Introduction<\/h3>\n<p>There is a saying out there that goes &#8216;what are you going to do with an FPGA, blink a bunch of LEDs?&#8217;<\/p>\n<p>Well&#8230; that saying is true.\u00a0 Today I purchased a breakout board for the Zynberry and found an excellent guide on how to do just that:<\/p>\n<ul>\n<li style=\"text-align: left;\"><a href=\"https:\/\/svenssonjoel.github.io\/writing\/blinkledzynq.pdf\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/svenssonjoel.github.io\/writing\/blinkledzynq.pdf<\/a><\/li>\n<\/ul>\n<p>But I am different and I am going to do more than just &#8216;blink a bunch of LEDs&#8217;.\u00a0 I am going to do something useful.\u00a0 &lt;= It&#8217;s a joke&#8230; hahaha&#8230; Okay, not only am I going to blink a bunch of LEDs by using an FPGA, I am going to do it by using LabVIEW FPGA *and* by having that LabVIEW &#8216;code&#8217; run on the Zynqberry, all at the same time!<\/p>\n<p>For the first part of this demo, I had to re-learn a bunch of things that I learned in my High School electronics class (thank you Bronx Science &#8211; <a href=\"http:\/\/www.bxscience.edu\" target=\"_blank\" rel=\"noopener noreferrer\">www.bxscience.edu<\/a>).\u00a0 What did I re-learn? How to power an LED without shorting the thing out&#8230; &lt;= that was another joke hahaha. I hope you laughed.\u00a0 Anyway, in the end, I used the breadboard provided by some electronics kit, along with three regular LEDs, one RGB LED, some push buttons and several 220 Ohm resistors.\u00a0 For testing I brought power to this breakout board by using a regular battery pack and the Breadboard 5v\/3v Power Supply Kit made by inland.\u00a0 This is not important right now, so I will cover what I did in another post.<\/p>\n<p>&lt;TODO: Insert the link here&#8230;&gt;<\/p>\n<h3>List of Parts:<\/h3>\n<p>I purchased everything from the Flushing Microcenter, which in my opinion has become a very suitable replacement for Radio Shack.<\/p>\n<ul>\n<li><a href=\"http:\/\/www.microcenter.com\" target=\"_blank\" rel=\"noopener noreferrer\">http:\/\/www.microcenter.com<\/a><\/li>\n<\/ul>\n<p>You don&#8217;t need to buy exactly what I did, but you will need the following components:<\/p>\n<ul>\n<li>2 x LEDS<\/li>\n<li>2 x220 Ohm Resistors<\/li>\n<li>A couple of jumper cables<\/li>\n<li>A Raspberry Pi 2 breakout board<\/li>\n<\/ul>\n<p>I got these components from the following kits:<\/p>\n<ul>\n<li>Inland Breadboard 5v\/3v Power Supply Kit<\/li>\n<li>Inland Electronic Parts Pack (KN3B)<\/li>\n<li>MCM Electronics 40 Pin GPIO Breakout and Cable for Raspberry Pi<\/li>\n<\/ul>\n<h3>Pictures of the Boxes:<\/h3>\n<p>Why pictures? Well, because these parts seem so generic that I can&#8217;t even find them online for sale.\u00a0<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LED_.Boxes_-scaled.jpg\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-912 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LED_.Boxes_-scaled.jpg\" alt=\"\" width=\"2560\" height=\"1133\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LED_.Boxes_-scaled.jpg 2560w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LED_.Boxes_-300x133.jpg 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LED_.Boxes_-1024x453.jpg 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LED_.Boxes_-768x340.jpg 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LED_.Boxes_-1536x680.jpg 1536w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LED_.Boxes_-2048x906.jpg 2048w\" sizes=\"auto, (max-width: 2560px) 100vw, 2560px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.40pin.GPIO_.Breakout.and_.Cable_.jpg\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-913 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.40pin.GPIO_.Breakout.and_.Cable_.jpg\" alt=\"\" width=\"1842\" height=\"1193\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.40pin.GPIO_.Breakout.and_.Cable_.jpg 1842w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.40pin.GPIO_.Breakout.and_.Cable_-300x194.jpg 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.40pin.GPIO_.Breakout.and_.Cable_-1024x663.jpg 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.40pin.GPIO_.Breakout.and_.Cable_-768x497.jpg 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.40pin.GPIO_.Breakout.and_.Cable_-1536x995.jpg 1536w\" sizes=\"auto, (max-width: 1842px) 100vw, 1842px\" \/><\/a><\/p>\n<h3>Simple Example<\/h3>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.One_.LED_-scaled.jpg\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-914 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.One_.LED_-scaled.jpg\" alt=\"\" width=\"2560\" height=\"1727\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.One_.LED_-scaled.jpg 2560w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.One_.LED_-300x202.jpg 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.One_.LED_-1024x691.jpg 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.One_.LED_-768x518.jpg 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.One_.LED_-1536x1036.jpg 1536w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.One_.LED_-2048x1381.jpg 2048w\" sizes=\"auto, (max-width: 2560px) 100vw, 2560px\" \/><\/a><\/p>\n<p>The TL;DR for this one is &#8211; Connect the positive pin of the power bank to a 220 Ohm resistor, then the resistor to the positive end of the LED, then the negative end of the LED to ground.\u00a0 Why? Because if you wire an LED directly to the +3.3V you will likely short it out.<\/p>\n<h3>The LabVIEW Part<\/h3>\n<p>Okay, so now that I gave myself a nice refresher on using electronics, while having fun, which is the most import part I then started to do something similar but with LabVIEW FPGA and the NI LabVIEW FPGA IP Export Utility.<\/p>\n<p>I created a LabVIEW FPGA project using LabVIEW 2020 (32-bit version) and added a target that uses a Zynq family FPGA such as the Real-Time Compact RIO part cRio-9063.\u00a0 The following screenshots should be sufficient if you have some LabVIEW FPGA experience.\u00a0 If you do not, you will need to get some.\u00a0 I would like to provide a more in-depth guide on that at some point.<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.01.Project.Only_..png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-923 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.01.Project.Only_..png\" alt=\"\" width=\"652\" height=\"778\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.01.Project.Only_..png 652w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.01.Project.Only_.-251x300.png 251w\" sizes=\"auto, (max-width: 652px) 100vw, 652px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.02.Front_.Panel_..png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-924 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.02.Front_.Panel_..png\" alt=\"\" width=\"1027\" height=\"494\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.02.Front_.Panel_..png 1027w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.02.Front_.Panel_.-300x144.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.02.Front_.Panel_.-1024x493.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.02.Front_.Panel_.-768x369.png 768w\" sizes=\"auto, (max-width: 1027px) 100vw, 1027px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.03.Block_.Diagram.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-925 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.03.Block_.Diagram.png\" alt=\"\" width=\"1564\" height=\"739\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.03.Block_.Diagram.png 1564w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.03.Block_.Diagram-300x142.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.03.Block_.Diagram-1024x484.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.03.Block_.Diagram-768x363.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.03.Block_.Diagram-1536x726.png 1536w\" sizes=\"auto, (max-width: 1564px) 100vw, 1564px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.04.Project.All_.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-926 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.04.Project.All_.png\" alt=\"\" width=\"2271\" height=\"1291\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.04.Project.All_.png 2271w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.04.Project.All_-300x171.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.04.Project.All_-1024x582.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.04.Project.All_-768x437.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.04.Project.All_-1536x873.png 1536w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.04.Project.All_-2048x1164.png 2048w\" sizes=\"auto, (max-width: 2271px) 100vw, 2271px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.05.Create.Build_.Specification.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-927 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.05.Create.Build_.Specification.png\" alt=\"\" width=\"975\" height=\"1342\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.05.Create.Build_.Specification.png 975w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.05.Create.Build_.Specification-218x300.png 218w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.05.Create.Build_.Specification-744x1024.png 744w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.05.Create.Build_.Specification-768x1057.png 768w\" sizes=\"auto, (max-width: 975px) 100vw, 975px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.06.Export.to_.Netlist.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-928 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.06.Export.to_.Netlist.png\" alt=\"\" width=\"843\" height=\"1095\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.06.Export.to_.Netlist.png 843w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.06.Export.to_.Netlist-231x300.png 231w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.06.Export.to_.Netlist-788x1024.png 788w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.LabVIEW.06.Export.to_.Netlist-768x998.png 768w\" sizes=\"auto, (max-width: 843px) 100vw, 843px\" \/><\/a><\/p>\n<p>\u00a0<\/p>\n<h3>LabVIEW FPGA IP Export Utility Section<\/h3>\n<p>So what does &#8220;Export VI to Netlist File&#8221; do? It creates two files.\u00a0 A Xilinx dcp file, which I believe stands for &#8220;design checkpoint&#8221;, and\u00a0 corresponding vhdl wrapper file for it.\u00a0 Now these 2 files have the same name, but with a different extension, cand this file name is like a C++ function that has been mangled.\u00a0 Which means that if you want to keep things simple, just call the VI something simple and short like &#8220;adder&#8221;, instead of &#8220;My NI LabVIEW to FPGA to Vivado Wrapper for blah blah blah&#8221;.\u00a0 Anyway, the design above generates two files that get placed in to the C:\\NIFPGA\\compilation directory.\u00a0 The name of the sub-directory will again follow some sort of name-mangling convention.\u00a0 For me I have:<\/p>\n<p>\u00a0<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zyn1berry_1.LabVIEW.Export.to_.Netlist.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-937 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zyn1berry_1.LabVIEW.Export.to_.Netlist.png\" alt=\"\" width=\"1888\" height=\"1157\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zyn1berry_1.LabVIEW.Export.to_.Netlist.png 1888w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zyn1berry_1.LabVIEW.Export.to_.Netlist-300x184.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zyn1berry_1.LabVIEW.Export.to_.Netlist-1024x628.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zyn1berry_1.LabVIEW.Export.to_.Netlist-768x471.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zyn1berry_1.LabVIEW.Export.to_.Netlist-1536x941.png 1536w\" sizes=\"auto, (max-width: 1888px) 100vw, 1888px\" \/><\/a><\/p>\n<p>\u00a0<\/p>\n<h3>Vivado Section<\/h3>\n<p>Now create a Vivado project and make sure you are using the same version of Vivado as LabVIEW is using.\u00a0 Since I am using LabVIEW 2020, the version of Vivado is 2019.\u00a0 You can use the version that is packaged with LabVIEW, or you can download it yourself.\u00a0 I chose to download it myself so I get whatever NI has decided or had to strip out as part of their agreement to distribute with LabVIEW.<\/p>\n<h4>Zynqberry Board Parts<\/h4>\n<p>You should install the Zynqberry board parts file.<\/p>\n<p>From the Trenz Electronics homepage for the Zynqberry:<\/p>\n<ul>\n<li><a href=\"https:\/\/wiki.trenz-electronic.de\/display\/PD\/TE0726+-+ZynqBerry\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/wiki.trenz-electronic.de\/display\/PD\/TE0726+-+ZynqBerry<\/a><\/li>\n<\/ul>\n<p>Download one of the Reference Designs for a version of Vivado close to 2019.1<\/p>\n<ul>\n<li><a href=\"https:\/\/shop.trenz-electronic.de\/Download\/?path=Trenz_Electronic\/Modules_and_Module_Carriers\/special\/TE0726\/Reference_Design\" target=\"_blank\" rel=\"noopener noreferrer\">https:\/\/shop.trenz-electronic.de\/Download\/?path=Trenz_Electronic\/Modules_and_Module_Carriers\/special\/TE0726\/Reference_Design<\/a><\/li>\n<\/ul>\n<p>Extract the zip file and look for the board_files directory, and it should contain two directories, in my case it is:<\/p>\n<ul>\n<li>TE0726<\/li>\n<li>TE0726_7S<\/li>\n<\/ul>\n<p>You want to copy these directories to your Vivado installation to the C:\\xilinx\\Vivado\\2019.1\\data\\boards\\board_files directory. My directory looks like this:<\/p>\n<p>\u00a0<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Vivado.Board_Parts.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-940 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Vivado.Board_Parts.png\" alt=\"\" width=\"1019\" height=\"732\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Vivado.Board_Parts.png 1019w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Vivado.Board_Parts-300x216.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Vivado.Board_Parts-768x552.png 768w\" sizes=\"auto, (max-width: 1019px) 100vw, 1019px\" \/><\/a><\/p>\n<h4>Vivado Create Project<\/h4>\n<p>\u00a0<\/p>\n<p>I hope you have some experience using Vivado, if not I will try to include enough information for you.\u00a0 (Please comment below if anything is unclear, just reference the picture # and the title heading)<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.01-Create.Project.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-942 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.01-Create.Project.png\" alt=\"\" width=\"1378\" height=\"1170\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.01-Create.Project.png 1378w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.01-Create.Project-300x255.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.01-Create.Project-1024x869.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.01-Create.Project-768x652.png 768w\" sizes=\"auto, (max-width: 1378px) 100vw, 1378px\" \/><\/a><\/p>\n<p>\u00a0<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.02-Project.Type_.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-943 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.02-Project.Type_.png\" alt=\"\" width=\"1378\" height=\"1170\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.02-Project.Type_.png 1378w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.02-Project.Type_-300x255.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.02-Project.Type_-1024x869.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.02-Project.Type_-768x652.png 768w\" sizes=\"auto, (max-width: 1378px) 100vw, 1378px\" \/><\/a><\/p>\n<p>\u00a0<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.03-Add.Sources-1.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-945 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.03-Add.Sources-1.png\" alt=\"\" width=\"1378\" height=\"1170\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.03-Add.Sources-1.png 1378w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.03-Add.Sources-1-300x255.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.03-Add.Sources-1-1024x869.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.03-Add.Sources-1-768x652.png 768w\" sizes=\"auto, (max-width: 1378px) 100vw, 1378px\" \/><\/a><\/p>\n<p>\u00a0<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.04-Add.Constraints.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-946 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.04-Add.Constraints.png\" alt=\"\" width=\"1378\" height=\"1170\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.04-Add.Constraints.png 1378w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.04-Add.Constraints-300x255.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.04-Add.Constraints-1024x869.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.04-Add.Constraints-768x652.png 768w\" sizes=\"auto, (max-width: 1378px) 100vw, 1378px\" \/><\/a><\/p>\n<p>\u00a0<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.05-Pick.Board_.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-947 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.05-Pick.Board_.png\" alt=\"\" width=\"1378\" height=\"1170\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.05-Pick.Board_.png 1378w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.05-Pick.Board_-300x255.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.05-Pick.Board_-1024x869.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.05-Pick.Board_-768x652.png 768w\" sizes=\"auto, (max-width: 1378px) 100vw, 1378px\" \/><\/a><\/p>\n<p>\u00a0<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.06-Project.Summary.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-948 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.06-Project.Summary.png\" alt=\"\" width=\"1378\" height=\"1170\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.06-Project.Summary.png 1378w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.06-Project.Summary-300x255.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.06-Project.Summary-1024x869.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.06-Project.Summary-768x652.png 768w\" sizes=\"auto, (max-width: 1378px) 100vw, 1378px\" \/><\/a><\/p>\n<p>\u00a0<\/p>\n<p>\u00a0<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.07-Empty.Project.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-950 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.07-Empty.Project.png\" alt=\"\" width=\"2979\" height=\"1837\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.07-Empty.Project.png 2979w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.07-Empty.Project-300x185.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.07-Empty.Project-1024x631.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.07-Empty.Project-768x474.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.07-Empty.Project-1536x947.png 1536w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.Vivado.07-Empty.Project-2048x1263.png 2048w\" sizes=\"auto, (max-width: 2979px) 100vw, 2979px\" \/><\/a><\/p>\n<p>\u00a0<\/p>\n<h4>Vivado Block Design<\/h4>\n<p>I hope you have created a Block Design before.\u00a0 It is cool. It reminds me somewhat of LabVIEW, but coming from a &#8216;text-based&#8217; programming point of view. Follow these pictures and create a Block Design in your Vivado project which will map to what occurs on the Zynqberry board.\u00a0 To the professional VHDL developers out there, yes, I am aware that I may not need to include the Zynq Processor.\u00a0 I say this only now&#8230; as I am writing this post.<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.01-Add.Source.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-956 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.01-Add.Source.png\" alt=\"\" width=\"780\" height=\"671\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.01-Add.Source.png 780w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.01-Add.Source-300x258.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.01-Add.Source-768x661.png 768w\" sizes=\"auto, (max-width: 780px) 100vw, 780px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.02.Add_.Or_.Create.Design.Sources.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-957 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.02.Add_.Or_.Create.Design.Sources.png\" alt=\"\" width=\"1472\" height=\"998\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.02.Add_.Or_.Create.Design.Sources.png 1472w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.02.Add_.Or_.Create.Design.Sources-300x203.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.02.Add_.Or_.Create.Design.Sources-1024x694.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.02.Add_.Or_.Create.Design.Sources-768x521.png 768w\" sizes=\"auto, (max-width: 1472px) 100vw, 1472px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.03.Create.File_.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-958\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.03.Create.File_.png\" alt=\"\" width=\"1472\" height=\"998\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.03.Create.File_.png 1472w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.03.Create.File_-300x203.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.03.Create.File_-1024x694.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.03.Create.File_-768x521.png 768w\" sizes=\"auto, (max-width: 1472px) 100vw, 1472px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.04.Create.A.Source.File_.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-961\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.04.Create.A.Source.File_.png\" alt=\"\" width=\"629\" height=\"432\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.04.Create.A.Source.File_.png 629w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.04.Create.A.Source.File_-300x206.png 300w\" sizes=\"auto, (max-width: 629px) 100vw, 629px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.05.File_.Name_.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-962\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.05.File_.Name_.png\" alt=\"\" width=\"1472\" height=\"998\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.05.File_.Name_.png 1472w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.05.File_.Name_-300x203.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.05.File_.Name_-1024x694.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.05.File_.Name_-768x521.png 768w\" sizes=\"auto, (max-width: 1472px) 100vw, 1472px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.06.Define.Module.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-963\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.06.Define.Module.png\" alt=\"\" width=\"1052\" height=\"753\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.06.Define.Module.png 1052w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.06.Define.Module-300x215.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.06.Define.Module-1024x733.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.06.Define.Module-768x550.png 768w\" sizes=\"auto, (max-width: 1052px) 100vw, 1052px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.07.After_.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-964\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.07.After_.png\" alt=\"\" width=\"1022\" height=\"790\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.07.After_.png 1022w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.07.After_-300x232.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Zynqberry_1.07.After_-768x594.png 768w\" sizes=\"auto, (max-width: 1022px) 100vw, 1022px\" \/><\/a><\/p>\n<h4><br \/>Add the LabVIEW Exported IP<\/h4>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_01.Add_.Source.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-968 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_01.Add_.Source.png\" alt=\"\" width=\"765\" height=\"650\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_01.Add_.Source.png 765w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_01.Add_.Source-300x255.png 300w\" sizes=\"auto, (max-width: 765px) 100vw, 765px\" \/><\/a><\/p>\n<h4><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_02.Add_.or_.Create.Design.Sources.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-969 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_02.Add_.or_.Create.Design.Sources.png\" alt=\"\" width=\"1472\" height=\"998\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_02.Add_.or_.Create.Design.Sources.png 1472w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_02.Add_.or_.Create.Design.Sources-300x203.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_02.Add_.or_.Create.Design.Sources-1024x694.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_02.Add_.or_.Create.Design.Sources-768x521.png 768w\" sizes=\"auto, (max-width: 1472px) 100vw, 1472px\" \/><\/a><\/h4>\n<h4><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_03.Add_.Files_.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-970 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_03.Add_.Files_.png\" alt=\"\" width=\"1472\" height=\"998\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_03.Add_.Files_.png 1472w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_03.Add_.Files_-300x203.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_03.Add_.Files_-1024x694.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_03.Add_.Files_-768x521.png 768w\" sizes=\"auto, (max-width: 1472px) 100vw, 1472px\" \/><\/a><\/h4>\n<h4><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_04.Select.Files_.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-971 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_04.Select.Files_.png\" alt=\"\" width=\"1352\" height=\"653\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_04.Select.Files_.png 1352w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_04.Select.Files_-300x145.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_04.Select.Files_-1024x495.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_04.Select.Files_-768x371.png 768w\" sizes=\"auto, (max-width: 1352px) 100vw, 1352px\" \/><\/a><\/h4>\n<h4><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_05.See_.the_.Files_.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-972 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_05.See_.the_.Files_.png\" alt=\"\" width=\"1472\" height=\"998\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_05.See_.the_.Files_.png 1472w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_05.See_.the_.Files_-300x203.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_05.See_.the_.Files_-1024x694.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_05.See_.the_.Files_-768x521.png 768w\" sizes=\"auto, (max-width: 1472px) 100vw, 1472px\" \/><\/a><\/h4>\n<h4><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_06.After_.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-973 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_06.After_.png\" alt=\"\" width=\"821\" height=\"880\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_06.After_.png 821w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_06.After_-280x300.png 280w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Add.LabVIEW.IP_06.After_-768x823.png 768w\" sizes=\"auto, (max-width: 821px) 100vw, 821px\" \/><\/a><\/h4>\n<h4>Add the LabVIEW Exported IP to the top-level VHDL Module<\/h4>\n<p>Modify the my_top_level.vhd file to look like this picture:<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Import.LabVIEW.IP_01.Add_.SourceZynqberry_Add.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-975 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Import.LabVIEW.IP_01.Add_.SourceZynqberry_Add.png\" alt=\"\" width=\"1539\" height=\"1406\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Import.LabVIEW.IP_01.Add_.SourceZynqberry_Add.png 1539w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Import.LabVIEW.IP_01.Add_.SourceZynqberry_Add-300x274.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Import.LabVIEW.IP_01.Add_.SourceZynqberry_Add-1024x936.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Import.LabVIEW.IP_01.Add_.SourceZynqberry_Add-768x702.png 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Import.LabVIEW.IP_01.Add_.SourceZynqberry_Add-1536x1403.png 1536w\" sizes=\"auto, (max-width: 1539px) 100vw, 1539px\" \/><\/a><\/p>\n<p>paste the following:<\/p>\n<table style=\"border-collapse: collapse; width: 100%;\">\n<tbody>\n<tr>\n<td style=\"width: 100%;\">\n<div><span style=\"font-family: inherit; font-size: inherit; font-weight: inherit; background-color: var(--go--color--background,0,0,100%); letter-spacing: var(--go--letter-spacing,normal);\">library IEEE;<\/span><\/div>\n<div>\n<div>use IEEE.STD_LOGIC_1164.ALL;<\/div>\n<div>\u00a0<\/div>\n<div>&#8212; Uncomment the following library declaration if using<\/div>\n<div>&#8212; arithmetic functions with Signed or Unsigned values<\/div>\n<div>&#8211;use IEEE.NUMERIC_STD.ALL;<\/div>\n<div>\u00a0<\/div>\n<div>&#8212; Uncomment the following library declaration if instantiating<\/div>\n<div>&#8212; any Xilinx leaf cells in this code.<\/div>\n<div>&#8211;library UNISIM;<\/div>\n<div>&#8211;use UNISIM.VComponents.all;<\/div>\n<div>\u00a0<\/div>\n<div>entity my_top_level is<\/div>\n<div>\u00a0 Port (<\/div>\n<div>\u00a0 \u00a0 GPIO_0_tri_i : in STD_LOGIC_VECTOR ( 7 downto 0 );<\/div>\n<div>\u00a0 \u00a0 GPIO_1_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 )<\/div>\n<div>);<\/div>\n<div>end my_top_level;<\/div>\n<div>\u00a0<\/div>\n<div>architecture Behavioral of my_top_level is<\/div>\n<div>\u00a0 component NiFpgaIPWrapper_LabVIEW_Echo is<\/div>\n<div>\u00a0 \u00a0 port (<\/div>\n<div>\u00a0 \u00a0 \u00a0 reset : in std_logic;<\/div>\n<div>\u00a0 \u00a0 \u00a0 enable_in : in std_logic;<\/div>\n<div>\u00a0 \u00a0 \u00a0 enable_out : out std_logic;<\/div>\n<div>\u00a0 \u00a0 \u00a0 enable_clr : in std_logic;<\/div>\n<div>\u00a0 \u00a0 \u00a0 ctrlind_00_Data_in_U8 : in std_logic_vector(7 downto 0);<\/div>\n<div>\u00a0 \u00a0 \u00a0 ctrlind_01_Data_out_U8 : out std_logic_vector(7 downto 0);<\/div>\n<div>\u00a0 \u00a0 \u00a0 Clk40 : in std_logic<\/div>\n<div>\u00a0 \u00a0 );<\/div>\n<div>\u00a0 end component NiFpgaIPWrapper_LabVIEW_Echo;<\/div>\n<div>\u00a0<\/div>\n<div>\u00a0 signal signal_clock: STD_LOGIC;<\/div>\n<div>\u00a0 signal echo_signal_enable_out: STD_LOGIC;<\/div>\n<div>\u00a0<\/div>\n<div>begin<\/div>\n<div>\u00a0<\/div>\n<div>ni_echo_i: component NiFpgaIPWrapper_LabVIEW_Echo<\/div>\n<div>\u00a0 port map(<\/div>\n<div>\u00a0 \u00a0 reset =&gt; &#8216;0&#8217;,<\/div>\n<div>\u00a0 \u00a0 enable_in =&gt; &#8216;1&#8217;,<\/div>\n<div>\u00a0 \u00a0 enable_out =&gt; echo_signal_enable_out,<\/div>\n<div>\u00a0 \u00a0 enable_clr =&gt; &#8216;0&#8217;,<\/div>\n<div>&#8212;\u00a0 \u00a0 ctrlind_00_Data_in_U8 =&gt; &#8220;00011100&#8221;,<\/div>\n<div>\u00a0 \u00a0 ctrlind_00_Data_in_U8 =&gt; GPIO_0_tri_i(7 downto 0),<\/div>\n<div>\u00a0 \u00a0 ctrlind_01_Data_out_U8 =&gt; GPIO_1_tri_o(7 downto 0),<\/div>\n<div>\u00a0 \u00a0 Clk40 =&gt; signal_clock<\/div>\n<div>\u00a0 );<\/div>\n<div>\u00a0<\/div>\n<div>end Behavioral;<\/div>\n<\/div>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h4>Add Master Constraints File<\/h4>\n<p>\u00a0<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Import.LabVIEW.IP_06.Constraints-1.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-1001\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Import.LabVIEW.IP_06.Constraints-1.png\" alt=\"\" width=\"1434\" height=\"1232\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Import.LabVIEW.IP_06.Constraints-1.png 1434w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Import.LabVIEW.IP_06.Constraints-1-300x258.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Import.LabVIEW.IP_06.Constraints-1-1024x880.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Import.LabVIEW.IP_06.Constraints-1-768x660.png 768w\" sizes=\"auto, (max-width: 1434px) 100vw, 1434px\" \/><\/a><\/p>\n<p>Or cut and paste the following:<\/p>\n<table style=\"border-collapse: collapse; width: 100%;\">\n<tbody>\n<tr>\n<td style=\"width: 100%;\">\n<div>\n<div># LVCMOS33 because we are using 3.3V<\/div>\n<div>set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_tri_i[*]}]<\/div>\n<div>\u00a0<\/div>\n<div># PULLDOWN low makes sure all unwired inputs are 0 or false<\/div>\n<div>set_property PULLDOWN TRUE [get_ports {GPIO_0_tri_i[*]}]<\/div>\n<\/div>\n<div>\u00a0<\/div>\n<div>set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_tri_i[*]}]<\/div>\n<div>set_property PACKAGE_PIN H14 [get_ports {GPIO_0_tri_i[7]}]<\/div>\n<div>set_property PACKAGE_PIN J13 [get_ports {GPIO_0_tri_i[6]}]<\/div>\n<div>set_property PACKAGE_PIN J15 [get_ports {GPIO_0_tri_i[5]}]<\/div>\n<div>set_property PACKAGE_PIN N14 [get_ports {GPIO_0_tri_i[4]}]<\/div>\n<div>set_property PACKAGE_PIN R15 [get_ports {GPIO_0_tri_i[3]}]<\/div>\n<div>set_property PACKAGE_PIN R13 [get_ports {GPIO_0_tri_i[2]}]<\/div>\n<div>set_property PACKAGE_PIN R12 [get_ports {GPIO_0_tri_i[1]}]<\/div>\n<div>set_property PACKAGE_PIN L12 [get_ports {GPIO_0_tri_i[0]}]<\/div>\n<div>\u00a0<\/div>\n<div>set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_1_tri_o[*]}]<\/div>\n<div>set_property PACKAGE_PIN K11 [get_ports {GPIO_1_tri_o[7]}]<\/div>\n<div>set_property PACKAGE_PIN K13 [get_ports {GPIO_1_tri_o[6]}]<\/div>\n<div>set_property PACKAGE_PIN L15 [get_ports {GPIO_1_tri_o[5]}]<\/div>\n<div>set_property PACKAGE_PIN L14 [get_ports {GPIO_1_tri_o[4]}]<\/div>\n<div>set_property PACKAGE_PIN M15 [get_ports {GPIO_1_tri_o[3]}]<\/div>\n<div>set_property PACKAGE_PIN L13 [get_ports {GPIO_1_tri_o[2]}]<\/div>\n<div>set_property PACKAGE_PIN M14 [get_ports {GPIO_1_tri_o[1]}]<\/div>\n<div>set_property PACKAGE_PIN P15 [get_ports {GPIO_1_tri_o[0]}]<\/div>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h4>Generate Bitstream<\/h4>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Generate.Bitstream-01.Click_.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-985 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Generate.Bitstream-01.Click_.png\" alt=\"\" width=\"954\" height=\"722\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Generate.Bitstream-01.Click_.png 954w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Generate.Bitstream-01.Click_-300x227.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Generate.Bitstream-01.Click_-768x581.png 768w\" sizes=\"auto, (max-width: 954px) 100vw, 954px\" \/><\/a><\/p>\n<p>\u00a0<\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Generate.Bitstream-02.Click_.Okay_.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-986\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Generate.Bitstream-02.Click_.Okay_.png\" alt=\"\" width=\"851\" height=\"338\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Generate.Bitstream-02.Click_.Okay_.png 851w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Generate.Bitstream-02.Click_.Okay_-300x119.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Generate.Bitstream-02.Click_.Okay_-768x305.png 768w\" sizes=\"auto, (max-width: 851px) 100vw, 851px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Generate.Bitstream-03.Proceed.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-987\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Generate.Bitstream-03.Proceed.png\" alt=\"\" width=\"771\" height=\"579\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Generate.Bitstream-03.Proceed.png 771w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Generate.Bitstream-03.Proceed-300x225.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Generate.Bitstream-03.Proceed-768x577.png 768w\" sizes=\"auto, (max-width: 771px) 100vw, 771px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Generate.Bitstream-04.Cancel.is_.Fine_.png\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-989\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Generate.Bitstream-04.Cancel.is_.Fine_.png\" alt=\"\" width=\"584\" height=\"545\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Generate.Bitstream-04.Cancel.is_.Fine_.png 584w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Generate.Bitstream-04.Cancel.is_.Fine_-300x280.png 300w\" sizes=\"auto, (max-width: 584px) 100vw, 584px\" \/><\/a><\/p>\n<h4>Program and Run!<\/h4>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-01.Open_.Hardware.Manager.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-991 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-01.Open_.Hardware.Manager.png\" alt=\"\" width=\"479\" height=\"482\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-01.Open_.Hardware.Manager.png 479w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-01.Open_.Hardware.Manager-298x300.png 298w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-01.Open_.Hardware.Manager-150x150.png 150w\" sizes=\"auto, (max-width: 479px) 100vw, 479px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-02.Open_.Target.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-992 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-02.Open_.Target.png\" alt=\"\" width=\"903\" height=\"440\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-02.Open_.Target.png 903w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-02.Open_.Target-300x146.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-02.Open_.Target-768x374.png 768w\" sizes=\"auto, (max-width: 903px) 100vw, 903px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-01.Open_.Hardware.Manager-1.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-993 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-01.Open_.Hardware.Manager-1.png\" alt=\"\" width=\"479\" height=\"482\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-01.Open_.Hardware.Manager-1.png 479w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-01.Open_.Hardware.Manager-1-298x300.png 298w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-01.Open_.Hardware.Manager-1-150x150.png 150w\" sizes=\"auto, (max-width: 479px) 100vw, 479px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-03.Auto_.Connect.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-994 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-03.Auto_.Connect.png\" alt=\"\" width=\"777\" height=\"470\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-03.Auto_.Connect.png 777w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-03.Auto_.Connect-300x181.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-03.Auto_.Connect-768x465.png 768w\" sizes=\"auto, (max-width: 777px) 100vw, 777px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-04.Program.Device.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-995 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-04.Program.Device.png\" alt=\"\" width=\"954\" height=\"337\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-04.Program.Device.png 954w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-04.Program.Device-300x106.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-04.Program.Device-768x271.png 768w\" sizes=\"auto, (max-width: 954px) 100vw, 954px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-05.Default.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-996 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-05.Default.png\" alt=\"\" width=\"602\" height=\"550\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-05.Default.png 602w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-05.Default-300x274.png 300w\" sizes=\"auto, (max-width: 602px) 100vw, 602px\" \/><\/a><\/p>\n<p><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-06.Program.Device.png\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-997 size-full\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-06.Program.Device.png\" alt=\"\" width=\"1035\" height=\"273\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-06.Program.Device.png 1035w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-06.Program.Device-300x79.png 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-06.Program.Device-1024x270.png 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Program_FPGA-06.Program.Device-768x203.png 768w\" sizes=\"auto, (max-width: 1035px) 100vw, 1035px\" \/><\/a><\/p>\n<h4>Pictures&#8230;.<\/h4>\n<p>\u00a0<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_01-Zynqberry.Closeup-1.jpg\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"768\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_01-Zynqberry.Closeup-1-1024x768.jpg\" alt=\"\" class=\"wp-image-1003\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_01-Zynqberry.Closeup-1-1024x768.jpg 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_01-Zynqberry.Closeup-1-300x225.jpg 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_01-Zynqberry.Closeup-1-768x576.jpg 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_01-Zynqberry.Closeup-1-1536x1152.jpg 1536w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_01-Zynqberry.Closeup-1.jpg 2000w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/a><\/figure>\n\n\n\n<figure class=\"wp-block-image size-large\"><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_02-Zynqberry.All_.Wired_.Up_.jpg\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"768\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_02-Zynqberry.All_.Wired_.Up_-1024x768.jpg\" alt=\"\" class=\"wp-image-1004\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_02-Zynqberry.All_.Wired_.Up_-1024x768.jpg 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_02-Zynqberry.All_.Wired_.Up_-300x225.jpg 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_02-Zynqberry.All_.Wired_.Up_-768x576.jpg 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_02-Zynqberry.All_.Wired_.Up_-1536x1152.jpg 1536w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_02-Zynqberry.All_.Wired_.Up_.jpg 2000w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/a><\/figure>\n\n\n\n<figure class=\"wp-block-image size-large\"><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_03-Zynqberry.One_.LED_.On_.jpg\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"768\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_03-Zynqberry.One_.LED_.On_-1024x768.jpg\" alt=\"\" class=\"wp-image-1005\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_03-Zynqberry.One_.LED_.On_-1024x768.jpg 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_03-Zynqberry.One_.LED_.On_-300x225.jpg 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_03-Zynqberry.One_.LED_.On_-768x576.jpg 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_03-Zynqberry.One_.LED_.On_-1536x1152.jpg 1536w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_03-Zynqberry.One_.LED_.On_.jpg 2000w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/a><\/figure>\n\n\n\n<figure class=\"wp-block-image size-large\"><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_04-Zynqberry.Two_.LEDs_.On_.jpg\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"768\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_04-Zynqberry.Two_.LEDs_.On_-1024x768.jpg\" alt=\"\" class=\"wp-image-1006\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_04-Zynqberry.Two_.LEDs_.On_-1024x768.jpg 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_04-Zynqberry.Two_.LEDs_.On_-300x225.jpg 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_04-Zynqberry.Two_.LEDs_.On_-768x576.jpg 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_04-Zynqberry.Two_.LEDs_.On_-1536x1152.jpg 1536w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_04-Zynqberry.Two_.LEDs_.On_.jpg 2000w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/a><\/figure>\n\n\n\n<figure class=\"wp-block-image size-large\"><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_05-Zynqberry.Another.View_.jpg\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"425\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_05-Zynqberry.Another.View_-1024x425.jpg\" alt=\"\" class=\"wp-image-1007\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_05-Zynqberry.Another.View_-1024x425.jpg 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_05-Zynqberry.Another.View_-300x125.jpg 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_05-Zynqberry.Another.View_-768x319.jpg 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_05-Zynqberry.Another.View_-1536x638.jpg 1536w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_05-Zynqberry.Another.View_.jpg 1915w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/a><\/figure>\n\n\n\n<figure class=\"wp-block-image size-large\"><a href=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_06-Zynqberry.Full_.View_.jpg\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"364\" src=\"http:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_06-Zynqberry.Full_.View_-1024x364.jpg\" alt=\"\" class=\"wp-image-1008\" srcset=\"https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_06-Zynqberry.Full_.View_-1024x364.jpg 1024w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_06-Zynqberry.Full_.View_-300x107.jpg 300w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_06-Zynqberry.Full_.View_-768x273.jpg 768w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_06-Zynqberry.Full_.View_-1536x545.jpg 1536w, https:\/\/fpganow.com\/wp-content\/uploads\/2020\/09\/Run_06-Zynqberry.Full_.View_.jpg 2000w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/a><\/figure>\n","protected":false},"excerpt":{"rendered":"<p>Source Code: https:\/\/github.com\/fpganow\/Blink_LEDS Introduction There is a saying out there that goes &#8216;what are you going to do with an FPGA, blink a bunch of LEDs?&#8217; Well&#8230; that saying is true.\u00a0 Today I purchased a breakout board for the Zynberry and found an excellent guide on how to do just that: https:\/\/svenssonjoel.github.io\/writing\/blinkledzynq.pdf But I am &#8230; <a title=\"Zynqberry with Breakout Board and LabVIEW\" class=\"read-more\" href=\"https:\/\/fpganow.com\/index.php\/2020\/09\/28\/zynqberry-with-breakout-board-and-labview\/\" aria-label=\"Read more about Zynqberry with Breakout Board and LabVIEW\">Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","footnotes":""},"categories":[1],"tags":[32,35],"class_list":["post-868","post","type-post","status-publish","format-standard","hentry","category-uncategorized","tag-fpga","tag-zynqberry","masonry-post","generate-columns","tablet-grid-50","mobile-grid-100","grid-parent","grid-50"],"_links":{"self":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/868","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/comments?post=868"}],"version-history":[{"count":85,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/868\/revisions"}],"predecessor-version":[{"id":1076,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/posts\/868\/revisions\/1076"}],"wp:attachment":[{"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/media?parent=868"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/categories?post=868"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/fpganow.com\/index.php\/wp-json\/wp\/v2\/tags?post=868"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}