I normally do not like the idea of New Years Resolutions as I think that every day is Day One of any plan, not January 1st of the next year. But it just so coincides that I have freed up some time to be able to spend more time on FPGANow.com again. So I went … Read more
Part 4 of the Smart FPGA Nic, dealing with the OrderBook has been published. Go here to see more: https://fpganow.com/index.php/part-4-order-book/ Related source code: https://github.com/fpganow/arty_bats/tree/main/labview/arty/orderbook As I make updates to the code, mainly to make it prettier and easier for others to follow, I will make new a post for each change detailing all changes.
I just created a ‘Page’ as opposed to a WordPress ‘Post’ documenting how I was able to parse BATS Market Data messages. This new style or format will be much better than my writing multiples posts. Easier for the reader to find, and easier for me to find and to update an article. Anyway, look … Read more
Related Source Repository: https://github.com/fpganow/vivado_scm Xilinx Vivado does not come with built-in source control. If you are a Visual Studio user, or a IntelliJ IDEA or eclipse user, you may be familiar with using some sort of IDE-related source code control. Vivado has a different paradigm for source control: Export commands to re-generate the project as … Read more
So my workflow is as follows: Create IP in NI LabVIEW FPGA Export via FPGA IP Export Tool Creates a VHDL wrapper (.vhd) Places IP in Design Checkpoint (.dcp) file Open my Vivado Block Design Use or update the VHDL wrapper that uses the Design Checkpoint Synthesis, Implementation, and Run The NI LabVIEW FPGA IP … Read more
I got something working – with live hardware plugged in to my network. I used the larger version of the Arty Artix-7 board, which cost $250 USD, and made my own custom reader for the LabVIEW FPGA Network library. I did not implement network writing features, nor do anything with the payload. Nevertheless, this is … Read more
So I am dealing with the following scenarios: Scenario 1 – Genesys Zynq with SYZYGY SFP I have the Genesys Zynq UltraScale+ MPSoC 3EG board that does not provide direct access to the PHY pins, but has a SYZYGY port that I have plugged in to the SZG-DUALSFP module with an SFP connector. Scenario 2 … Read more
Here is the new plan: Step 1 – Create a design using a MicroBlaze processing system, enable a UART connection and listen on an AXI FIFO and dump packets to the screen as they are received in chunks of X bytes. Step 2 – Insert some LabVIEW FPGA code to send one packet of data … Read more
I no longer have to look into figuring out how to code up or wire up the SZG-DUALSFP daughter board to the Digilent Genesys Zynq UltraScale MPSoC+ board. Why? Because I have a really old board that cost only $99 dollars that gives me direct access to the pins of an old 10/100 MBit PHY! … Read more
So I spent some time to rebuild the out-of-box demo for the Genesys Zynq UltraScale MPSoC+ board. Not everything worked for me right away, so I made this post to include all the things I did to get it to work.: My system: Windows 10 Windows Subsystem for Linux 2 Ubuntu 18.04 (<= Ubuntu 20 … Read more