I want to use an FPGA Now!

BATS.Parser The BATS.Parser has the following interface: Source Code: LabVIEW FPGA: https://github.com/fpganow/cboe_pitch_lv_fpga/tree/main/cboe_pitch/fpga/bats.parser LabVIEW Host Tests: https://github.com/fpganow/cboe_pitch_lv_fpga/tree/main/cboe_pitch/host/bats.parser Inputs: Reset [Bool] Data [U8[8]] Data.Valid [Bool] Ready.For.Debug [Bool] Ready.For.OrderBook.Command [Bool] Outputs: Ready.For.Udp.Input [Bool] Debug.Element [U64] Debug.Valid [Bool] OrderBook.Command OrderBook.Command.Type [Cluster] Side [U8] Order Id [U64] Quantity [U32] Symbol [U64] Price [U64] Executed Quantity [U32] Canceled Quantity [U32] Remaining Quantity [U32] Seconds [U64] Nanoseconds [U64] OrderBook.Command.Valid [Bool] The BATS.Parser IP is expecting UDP (or TCP) application-level data coming from …

I have spent a lot of my free time developing this over the past 4-5 months.  I am busy working on an actual 'demo', so I will be brief.  The code for a BATS/CBOE Pitch message parser/feed handler is ready.  If you know LabVIEW, you are lucky, if you don't, you will have to watch an upcoming video of mine and to follow along closely… If you have LabVIEW, (you can download a free evaluation …

I spent some time re-organizing this site to make it easier on the eye, easier to navigate and to be more organized in general. I also figured out a way to run this site using Docker with a MariaDB backend that I can easily back up, download to any of my home mac or windows desktops, run it locally, make a lot of changes and re-upload it when necessary.  Maybe I should make a post …

Part 4 of the Smart FPGA Nic, dealing with the OrderBook has been published. Go here to see more: https://fpganow.com/index.php/part-4-order-book/ Related source code: https://github.com/fpganow/arty_bats/tree/main/labview/arty/orderbook As I make updates to the code, mainly to make it prettier and easier for others to follow, I will make new a post for each change detailing all changes.  

I just created a 'Page' as opposed to a WordPress 'Post' documenting how I was able to parse BATS Market Data messages. This new style or format will be much better than my writing multiples posts.  Easier for the reader to find, and easier for me to find and to update an article. Anyway, look above, under the "SMART 'FPGA-NIC'" menu above to find Part 2: Parse BATS Messages in an FPGA. (I never made …

Related Source Repository: https://github.com/fpganow/vivado_scm Xilinx Vivado does not come with built-in source control.  If you are a Visual Studio user, or a IntelliJ IDEA or eclipse user, you may be familiar with using some sort of IDE-related source code control. Vivado has a different paradigm for source control: Export commands to re-generate the project as a tcl script. Add tcl and all related files to source-control After I tried following a lot of guides that …

So my workflow is as follows: Create IP in NI LabVIEW FPGA Export via FPGA IP Export Tool Creates a VHDL wrapper (.vhd) Places IP in Design Checkpoint (.dcp) file Open my Vivado Block Design Use or update the VHDL wrapper that uses the Design Checkpoint Synthesis, Implementation, and Run The NI LabVIEW FPGA IP Export utility provides you with 2 files, a design checkpoint and a wrapper file to use for instantiating your IP …

I got something working – with live hardware plugged in to my network. I used the larger version of the Arty Artix-7 board, which cost $250 USD, and made my own custom reader for the LabVIEW FPGA Network library.  I did not implement network writing features, nor do anything with the payload.  Nevertheless, this is a Proof-of-Concept and can be used to make a nice FPGA accelerated network application. Anyway, follow these instructions if you …

So I am dealing with the following scenarios: Scenario 1 – Genesys Zynq with SYZYGY SFP I have the Genesys Zynq UltraScale+ MPSoC 3EG board that does not provide direct access to the PHY pins, but has a SYZYGY port that I have plugged in to the SZG-DUALSFP module with an SFP connector. Scenario 2 – Arty A7 Artix-7 with 10/100 Mbit PHY I have the Arty A7 Artx-7 FPGA Development Board that gives me …

Here is the new plan: Step 1 – Create a design using a MicroBlaze processing system, enable a UART connection and listen on an AXI FIFO and dump packets to the screen as they are received in chunks of X bytes. Step 2 – Insert some LabVIEW FPGA code to send one packet of data every second. Step 3 – Replace this LabVIEW FPGA code to listen to the MII Ethernet interface pins and to …

I no longer have to look into figuring out how to code up or wire up the SZG-DUALSFP daughter board to the Digilent Genesys Zynq UltraScale MPSoC+ board. Why? Because I have a really old board that cost only $99 dollars that gives me direct access to the pins of an old 10/100 MBit PHY! That's the Arty Artix-35T mini board! Anyway… I found a corresponding NI "no longer national instruments" board that targets the …

So I spent some time to rebuild the out-of-box demo for the Genesys Zynq UltraScale MPSoC+ board.  Not everything worked for me right away, so I made this post to include all the things I did to get it to work.: My system: Windows 10 Windows Subsystem for Linux 2 Ubuntu 18.04 (<= Ubuntu 20 does not work unless you make a lot of changes) References: Schematics https://reference.digilentinc.com/_media/reference/programmable-logic/genesys-zu/genesys_zu-3eg_sch_public.pdf Official Documentation from Digilent Official Getting Started …

I went to the Opal Kelly website again and noticed that there are a lot of menu options that I previously did not notice at the top menu. I found a sample board that uses their SZG-DUALSFP board: https://opalkelly.com/products/xem7320/ So now I can read the documentation for this board and be on my way! I also had some fun reading the specification documents for the SYZYGY specification, the SZG-DUALSFP board, and for the Finisar Tranceiver …

So I have the Genesys Zynq UltraScale + MPSoC board, I bought the SZG-DUALSFP from Opel Kelly, and I want to figure out how to wire this thing up. What pin goes where? I dunno.  I spent some time reading the SFP+ specification.  Everything makes sense.  Then I read through the SYZYGY specification.  Again, things make sense. So what does the interface look like? Anybody know? One though is to look at a sample from …

After my previous post showing how to use the NI LabVIEW FPGA IP Export Utility to run LabVIEW FPGA code on a Zynqberry (http://fpganow.com/index.php/2020/09/28/zynqberry-with-breakout-board-and-labview/), I continued following the examples I could find on the internet and was able to connect to the board by using the PS (Processing System) built-int UART, and to communicate to the GPIO by using C code. Then I wanted to access the PHY or the ETH pins directly and to …

Source Code: https://github.com/fpganow/Blink_LEDS Introduction There is a saying out there that goes 'what are you going to do with an FPGA, blink a bunch of LEDs?' Well… that saying is true.  Today I purchased a breakout board for the Zynberry and found an excellent guide on how to do just that: https://svenssonjoel.github.io/writing/blinkledzynq.pdf But I am different and I am going to do more than just 'blink a bunch of LEDs'.  I am going to do …

So I followed the Zynqberry tutorial here: https://www.knitronics.com/the-zynqberry-patch/getting-started-with-the-zynqberry-in-vivado-2018-2 And was able to get a basic Xilinx SDK application working on my Zynqberry, but with a twist… I used the NI LabVIEW IP Export tool to incorporate some LabVIEW code.  For now a simple adder that just adds 2 8-bit unsigned integers and outputs a 16-bit unsigned integer. Anyway, the key takeaways are: Follow the tutorial exactly and re-read it in case you have any confusion …

For those unfamiliar with the FIX protocol, see: https://en.wikipedia.org/wiki/Financial_Information_eXchange https://www.fixtrading.org/ The FIX Protocol transfers data uncompressed and in ASCII form.  The following data types are transferred like so: Integer Value To send the Integer 1,423, the TCP stream would look like this: Index ASCII Hex 0 '1' 0x31 1 '4' 0x34 2 '2' 0x32 3 '3' 0x33 Date Time Value To send the Date Time value pair "June 4th, 1998 2:58:48 PM", the TCP stream …

[Updated]: It turns out there are 2 editions of this board, and it looks like the premium one with a 10 Gigabit SFP+ connector is not yet available in the USA.  However, I did some research and the lesser version of this board – the 3EV – has a SYZYGY connector, which supports SFP+ peripherals. So I ordered these 2 accessories and am awaiting a response from the manufacturer in case they actually do have …

I did some research looking for existing TCP/IP FPGA Cores.  There are two basic types – 10 Gigabit and non-10 Gigabit.  There is also a range of free and commercial solutions out there, and I'm sure the usual caveats apply.  Free = no documentation or support, Commercial = super expensive.  Anyway, here is what I discovered: The most important thing is that data comes in using an AXI4-Lite or similar interface.  What is an AXI4-Lite …