How to Parse BATS Market Data Messages
I just created a ‘Page’ as opposed to a WordPress ‘Post’ documenting how I was able to parse BATS Market…
Xilinx Vivado and Source Control
Related Source Repository: https://github.com/fpganow/vivado_scm Xilinx Vivado does not come with built-in source control. If you are a Visual Studio user,…
Dealing with the Vivado [DRC INBB-3]’ Black Box Instances’ issue
So my workflow is as follows: Create IP in NI LabVIEW FPGA Export via FPGA IP Export Tool Creates a…
Okay, Parsing UDP in LabVIEW FPGA Works
I got something working – with live hardware plugged in to my network. I used the larger version of the…
Vivado Error [Opt 31-67], and How I Fixed It.
So I am dealing with the following scenarios: Scenario 1 – Genesys Zynq with SYZYGY SFP I have the Genesys…
Plans Using Arty Artix-7
Here is the new plan: Step 1 – Create a design using a MicroBlaze processing system, enable a UART connection…
And Another Alternative
I no longer have to look into figuring out how to code up or wire up the SZG-DUALSFP daughter board…
Rebuilding Genesys Zynq UltraScale MPSoC+ Out of Box Demo
So I spent some time to rebuild the out-of-box demo for the Genesys Zynq UltraScale MPSoC+ board. Not everything worked…
SZG-DUALSFP Update
I went to the Opal Kelly website again and noticed that there are a lot of menu options that I…
SZG-DUALSFP Howto?
So I have the Genesys Zynq UltraScale + MPSoC board, I bought the SZG-DUALSFP from Opel Kelly, and I want…