BATS/CBOE Pitch Feed Handler/Normalizer is Ready

I have spent a lot of my free time developing this over the past 4-5 months.  I am busy working on an actual ‘demo’, so I will be brief.  The code for a BATS/CBOE Pitch message parser/feed handler is ready.  If you know LabVIEW, you are lucky, if you don’t, you will have to watch an upcoming video of mine and to follow along closely…

If you have LabVIEW, (you can download a free evaluation from clone this repository and open the project:

This project does the following:

  • Normalized BATS/CBOE Pitch Market Data Messages into a single/normalized format
  • Filters out all messages except those based on a watchlist of securities that you specify during FPGA startup.
    • Yes, this means that the core maintains a sorted list of all order id’s in block ram in order to be able to check each message order id before deciding on whether or not to filter that message out.  The algorithm is currently very crude, but hey, if you want a hashmap, you are going to have to hire me!
    • And yes, if the quantity for a specific Order Id becomes zero – as a result of an order modify, reduce, delete, or executed message, that order will be deleted from block ram.


So I have been seeing that a lot of Market Data Feed Handlers / Ticker Plants having issues with latency whenever the load is too great.  So with this core, you can filter out all messages that are not related to the Ticker/tickers that you are not interested in, which should cause your TickerPlant to have less messages to handle/filter out.

How can you use this?

You can use this core to watch a specific list of securities, and to have only those messages sent to another core that will do the calculation that you want – maintain a list of orders, detect signals…etc And then send the appropriate signal to the rest of your trading infrastructure when necessary.  I am currently working on adding a 3rd component to this project – an algo folder – that will watch a specific security for specific parameters.

Upon opening the project you will see:

Open the code up and browse through the files.  All in all, there are 2 components:

    • – wrapper to enable testing
    • – wrapper for IP Export (vhdl/verilog friendly)
    • – wrapper to enable testing
    • – wrapper for IP Export (vhdl/verilog friendly) <= Not ready yet, working on it now…



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