Part 4 – OrderBook Now Published

Part 4 of the Smart FPGA Nic, dealing with the OrderBook has been published. Go here to see more: Related source code: As I make updates to the code, mainly to make it prettier and easier for others to follow, I will make new a post for each change detailing all changes.  

Xilinx Vivado and Source Control

Related Source Repository: Xilinx Vivado does not come with built-in source control.  If you are a Visual Studio user, or a IntelliJ IDEA or eclipse user, you may be familiar with using some sort of IDE-related source code control. Vivado has a different paradigm for source control: Export commands to re-generate the project as … Read more

Okay, Parsing UDP in LabVIEW FPGA Works

I got something working – with live hardware plugged in to my network. I used the larger version of the Arty Artix-7 board, which cost $250 USD, and made my own custom reader for the LabVIEW FPGA Network library.  I did not implement network writing features, nor do anything with the payload.  Nevertheless, this is … Read more

Plans Using Arty Artix-7

Here is the new plan: Step 1 – Create a design using a MicroBlaze processing system, enable a UART connection and listen on an AXI FIFO and dump packets to the screen as they are received in chunks of X bytes. Step 2 – Insert some LabVIEW FPGA code to send one packet of data … Read more

And Another Alternative

I no longer have to look into figuring out how to code up or wire up the SZG-DUALSFP daughter board to the Digilent Genesys Zynq UltraScale MPSoC+ board. Why? Because I have a really old board that cost only $99 dollars that gives me direct access to the pins of an old 10/100 MBit PHY! … Read more


I went to the Opal Kelly website again and noticed that there are a lot of menu options that I previously did not notice at the top menu. I found a sample board that uses their SZG-DUALSFP board: XEM7320 So now I can read the documentation for this board and be on my way! I … Read more