I made a quick YouTube playlist describing how to use the IP Integration Node to import:
- a single vhdl file from a Vivado project via a Netlist (.edn) file
- a single vhdl file from a Vivado project via a Design Checkpoint (.dcp) file
- a block design with custom Xilinx IP (AdderSubtractor) from a Vivado project via a Design Checkpoint (.dcp) file
I made a YouTube playlist:
- https://www.youtube.com/watch?v=oZ_Xy_TYXHw&list=PLRkNZWVdUmb-6_pEby_dkiIdRa-UOXL4I
You can browse the source code related to the project here:
- https://github.com/fpganow/labview_ip_node/tree/main/labview