Full Blog History

How to use LabVIEW FPGA IP Integration Node

I made a quick YouTube playlist describing how to use the IP Integration Node to import: a single vhdl file from a Vivado project via a Netlist (.edn) file a single vhdl file from a Vivado project via a Design Checkpoint (.dcp) file a block design with custom Xilinx IP (AdderSubtractor) from a Vivado project … Read more

BATS/CBOE Pitch Feed Handler/Normalizer is Ready

I have spent a lot of my free time developing this over the past 4-5 months.  I am busy working on an actual ‘demo’, so I will be brief.  The code for a BATS/CBOE Pitch message parser/feed handler is ready.  If you know LabVIEW, you are lucky, if you don’t, you will have to watch … Read more

New Theme

I spent some time re-organizing this site to make it easier on the eye, easier to navigate and to be more organized in general. I also figured out a way to run this site using Docker with a MariaDB backend that I can easily back up, download to any of my home mac or windows … Read more

Part 4 – OrderBook Now Published

Part 4 of the Smart FPGA Nic, dealing with the OrderBook has been published. Go here to see more: https://fpganow.com/index.php/part-4-order-book/ Related source code: https://github.com/fpganow/arty_bats/tree/main/labview/arty/orderbook As I make updates to the code, mainly to make it prettier and easier for others to follow, I will make new a post for each change detailing all changes.  

Xilinx Vivado and Source Control

Related Source Repository: https://github.com/fpganow/vivado_scm Xilinx Vivado does not come with built-in source control.  If you are a Visual Studio user, or a IntelliJ IDEA or eclipse user, you may be familiar with using some sort of IDE-related source code control. Vivado has a different paradigm for source control: Export commands to re-generate the project as … Read more

Okay, Parsing UDP in LabVIEW FPGA Works

I got something working – with live hardware plugged in to my network. I used the larger version of the Arty Artix-7 board, which cost $250 USD, and made my own custom reader for the LabVIEW FPGA Network library.  I did not implement network writing features, nor do anything with the payload.  Nevertheless, this is … Read more

Vivado Error [Opt 31-67], and How I Fixed It.

So I am dealing with the following scenarios: Scenario 1 – Genesys Zynq with SYZYGY SFP I have the Genesys Zynq UltraScale+ MPSoC 3EG board that does not provide direct access to the PHY pins, but has a SYZYGY port that I have plugged in to the SZG-DUALSFP module with an SFP connector. Scenario 2 … Read more