Full Blog History

How I Tested an FPGA-based BATS Parser using Python

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LabVIEW FPGA Implementation of BATS PITCH I implemented a CBOE / BATS Market Data Parser by using LabVIEW FPGA, following the specification from the exchange: US Equities/Options Multicast Depth of Book (PITCH) Specification https://www.cboe.com/us/equities/support/technical/ https://cdn.cboe.com/resources/membership/US_EQUITIES_OPTIONS_MULTICAST_PITCH_SPECIFICATION.pdf to be more precise the parsing of most of the message types (no Options support) using LabVIEW FPGA a LabVIEW … Read more

Vivado Simulator with Python Code

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I know that Python is growing and growing in popularity… I hear it is more popular than learning French, at least according to this article: https://www.ocadogroup.com/media/press-releases/python-overtakes-french-most-popular-language-taught-primary-schools/ So I found this python module pysv, that advertises that it allows you to call Python from your SystemVerilog code: https://github.com/Kuree/pysv As of today – January 3rd, 2024 – … Read more

Error While Running Vivado Simulation on Ubuntu 22.04

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So I was recently playing around with DPI (Direct Programming Interface) in Vivado Simulator.  My goal is to call some python code that I wrote that will generate valid BATS messages, pass that data into my IP, and check the parsed code coming out is correct. After reading through the Xilinx/AMD documentation, I went ahead … Read more

Vivado Hangs during Installation on WSL/Linux

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Long story, but I decided to try out/start using Vivado using Linux. After confirming that X11 was working on my WSL installation of Ubuntu 22.04, I decided to download the latest version of Vivado and to install it for Linux. During the installation, towards the end the installation hangs at “Generating installed device list” Xilinx/AMD … Read more

How to use LabVIEW FPGA IP Integration Node

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I made a quick YouTube playlist describing how to use the IP Integration Node to import: a single vhdl file from a Vivado project via a Netlist (.edn) file a single vhdl file from a Vivado project via a Design Checkpoint (.dcp) file a block design with custom Xilinx IP (AdderSubtractor) from a Vivado project … Read more

BATS/CBOE Pitch Feed Handler/Normalizer is Ready

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I have spent a lot of my free time developing this over the past 4-5 months.  I am busy working on an actual ‘demo’, so I will be brief.  The code for a BATS/CBOE Pitch message parser/feed handler is ready.  If you know LabVIEW, you are lucky, if you don’t, you will have to watch … Read more

New Theme

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I spent some time re-organizing this site to make it easier on the eye, easier to navigate and to be more organized in general. I also figured out a way to run this site using Docker with a MariaDB backend that I can easily back up, download to any of my home mac or windows … Read more

Part 4 – OrderBook Now Published

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Part 4 of the Smart FPGA Nic, dealing with the OrderBook has been published. Go here to see more: https://fpganow.com/index.php/part-4-order-book/ Related source code: https://github.com/fpganow/arty_bats/tree/main/labview/arty/orderbook As I make updates to the code, mainly to make it prettier and easier for others to follow, I will make new a post for each change detailing all changes.