Vivado Simulator with Python Code

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I know that Python is growing and growing in popularity… I hear it is more popular than learning French, at least according to this article:

So I found this python module pysv, that advertises that it allows you to call Python from your SystemVerilog code:

As of today – January 3rd, 2024 – it has a few issues:

  • Poor windows support
  • No support for passing native Python lists
    • This issue says that lists are now supported:
      • https://github.com/Kuree/pysv/issues/24

Anyway, I was able to take my BATS python library:

And using the pysv library, call it from my SystemVerilog test bench.  Now since LabVIEW FPGA IP Export exports an encrypted synthesized netlist, I could not use a normal simulation scripted workflow (or rather, I could not figure it out), but instead I ended up creating a project using the Vivado User Interface, then running synthesis and  a Post-Synthesis Functional Simulation and by then copying the compile.sh, elaborate.sh, and simulate.sh scripts out.  I am still cleaning up my code, but long story short I was able to:

  • Call functions in the cboe_pitch library such as ‘get_time’ to get the bytes for a BATS Time message
  • Return a custom object that wraps a Python list into a custom object
  • Dump the elements to the screen using the Vivado Simulator – both from the command line and from the User Interface.

Now I am cleaning up the scripts and Makefile.  I want it to be simple, both to use and understand and to replicate on other projects.

Code lives here:

https://github.com/fpganow/Market.Data.Bats.Parser

Just check the Makefile, which is where I will have rules that fall under the categories of:

  • compile
    • compile python bindings
  • elaborate
  • simulate
    • Regular simulation
    • Simulation with a waveform window popping up at the end

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