john Ever since I started developing this LabVIEW FPGA project that uses a MicroBlaze soft processor to process TCP streams, I have learned a lot and can comment on the pros and cons of using LabVIEW FPGA vs using a traditional Xilinx/Altera based FPGA development approach. For starters, LabVIEW FPGA blows every single other FPGA development … Read more
So here is the most simple, FPGA-based Network Interface Card that I know of. This application will start Port 0 of the 10 Gigabit Network interface that is provided by the PXIe-6592R (http://www.ni.com/en-us/support/model.pxie-6592.html) board by National Instruments, and will allow you to do any of the following: Check if any new ethernet frames have been received, and … Read more
I finished writing an application that exercises the first Port of the 10 Gigabit Ethernet Interface that is provided with the National Instruments PXIe-6592R board and as I started taking manual screenshots via the LabVIEW “File->Print” option I began to ponder, can this be done more easily? Or dare I say it “programmatically”? The LabVIEW … Read more
I am getting real close to finishing my proof-of-concept FPGA-based network card that is based on the PXIe-6592 National Instruments Board which uses the Kinex-7 410t FPGA chip by Xilinx, and has 2GB of DDR3 RAM. Using the Arty Arix board, I was able to make sure that the MicroBlaze code running the lwIP TCP/IP … Read more
What is the product of 0x9D0BF6FDAC70AB52 and 0x6408F6540A1384CB? Well, according to LabVIEW for Windows, the answer is 0x2D90DE07C0C42206. According to C++ on OSX (without any optimizations, usage of Intel Intrinsic functions), the answer is also 0x2D90DE07C0C42206. The real answer is… 0x3D5E2BF7DCBCA6622D90DE07C0C42206. How do you get this number? You have to use compiler intrinsics, or calculate this value … Read more
So I wanted to implement a simple, stripped down version of the open-source lightweight IP stack “lwIP” (https://savannah.nongnu.org/projects/lwip/) inside my LabVIEW FPGA project that I can handle TCP and UDP data streams. I do not have a lot of experience with this, and I found that building such a project inside Vivado would take around … Read more
I spent some time analyzing the Monero CryptoCurrency source code to understand the algorithm, how it works and to see if it is doable with an FPGA via LabVIEW for FPGA, our secret weapon. I learned that there are 4 steps to the Monero “CryptoNight” algorithm and that step 3 is the part that does … Read more
So I wanted to mention that I have all of my LabVIEW (and Vivado) code saved on a RAID-1 mirrored location on my network. From each of my workstations, I map the same network location to my Z drive. This way any and all issues of LabVIEW referring to absolute paths goes away. I do … Read more
So I have figured out how to use the MicroBlaze Core with an AXI-Stream FIFO, and I have also figured out how to export a project from Vivado by using the Vivado “Write Project TCL” option. See the following project: https://github.com/JohnStratoudakis/LabVIEW_Fpga/tree/master/06_MicroBlaze/04_lwIP_Ex You have to re-generate the Vivado Project and create a new SDK workspace in … Read more
I just uploaded some code to GitHub that is a full demonstration on how to use LabVIEW FPGA 2017, the MicroBlaze MCS core and the IO Bus that is attached to the MicroBlaze MCS. Clone the following repository: https://github.com/JohnStratoudakis/LabVIEW_Fpga/tree/master/05_MicroBlaze_Mcs/02_MicroBlaze_Mcs_IO_Bus and open the LabVIEW project: https://github.com/JohnStratoudakis/LabVIEW_Fpga/blob/master/05_MicroBlaze_Mcs/02_MicroBlaze_Mcs_IO_Bus/02_MicroBlaze_Mcs_IO_Bus.lvproj Look at the Vivado 2015.4 project: https://github.com/JohnStratoudakis/LabVIEW_Fpga/blob/master/05_MicroBlaze_Mcs/02_MicroBlaze_Mcs_IO_Bus/MicroBlaze_Mcs_IO_Bus/MicroBlaze_Mcs_IO_Bus.xpr And finally, using … Read more