Coding Standards Matter…

I have wired up the components of my 10 Gigabit FPGA Accelerated Network card with great care, and I decided to have my “tester” application skip the lwIP stack and to pass the received packet directly to the host for testing/verification purposes. Everything was checking out fine, the LabVIEW code looked flawless, the interface to … Read more

10 Gigabit FPGA-based Network Card

So here is the most simple, FPGA-based Network Interface Card that I know of. This application will start Port 0 of the 10 Gigabit Network interface that is provided by the PXIe-6592R (http://www.ni.com/en-us/support/model.pxie-6592.html) board by National Instruments, and will allow you to do any of the following: Check if any new ethernet frames have been received, and … Read more

10 Gigabit FPGA-based Network Code Coming Soon

I am getting real close to finishing my proof-of-concept FPGA-based network card that is based on the PXIe-6592 National Instruments Board which uses the Kinex-7 410t FPGA chip by Xilinx, and has 2GB of DDR3 RAM. Using the Arty Arix board, I was able to make sure that the MicroBlaze code running the lwIP TCP/IP … Read more

How to Multiply 64 bit Numbers in LabVIEW

What is the product of 0x9D0BF6FDAC70AB52 and 0x6408F6540A1384CB?  Well, according to LabVIEW for Windows, the answer is 0x2D90DE07C0C42206.  According to C++ on OSX (without any optimizations, usage of Intel Intrinsic functions), the answer is also 0x2D90DE07C0C42206. The real answer is…  0x3D5E2BF7DCBCA6622D90DE07C0C42206. How do you get this number? You have to use compiler intrinsics, or calculate this value … Read more

Some Time with the Arty Arix-7 35T Digilent Board

So I wanted to implement a simple, stripped down version of the open-source lightweight IP stack “lwIP” (https://savannah.nongnu.org/projects/lwip/) inside my LabVIEW FPGA project that I can handle TCP and UDP data streams. I do not have a lot of experience with this, and I found that building such a project inside Vivado would take around … Read more

More Code Posted to Github

So I have figured out how to use the MicroBlaze Core with an AXI-Stream FIFO, and I have also figured out how to export a project from Vivado by using the Vivado “Write Project TCL” option. See the following project: https://github.com/JohnStratoudakis/LabVIEW_Fpga/tree/master/06_MicroBlaze/04_lwIP_Ex You have to re-generate the Vivado Project and create a new SDK workspace in … Read more

Hello FPGA

So I want to use an FPGA.  I don’t want to spend thousands of hours reading through manuals, learning VHDL or the “easier” Verilog, and I don’t want to spend forever picking the right hardware, accessories, boards, installing drivers, getting it to work with my operating system…etc I heard LabVIEW for FPGA is a great … Read more