Some Time with the Arty Arix-7 35T Digilent Board

So I wanted to implement a simple, stripped down version of the open-source lightweight IP stack “lwIP” ( inside my LabVIEW FPGA project that I can handle TCP and UDP data streams.

I do not have a lot of experience with this, and I found that building such a project inside Vivado would take around 3 hours to simulate with all of the source code of the lwIP project embedded in the elf file.

I ended up purchasing a $99 board from Digilent that uses an Artix-7 35T board:

On this board I was able to run and debug the lwIP source code so that I could figure out how to use it with my configuration.  I creatd a public github repository with this source code, so if you happen to be trying to learn how to use the MicroBlaze processor with this board, check out:

Enjoy and I will be working on integrating this lwIP source code in to my LabVIEW FPGA project now.

Issues with LabVIEW and Lack of Relative Directory References

So I wanted to mention that I have all of my LabVIEW (and Vivado) code saved on a RAID-1 mirrored location on my network.  From each of my workstations, I map the same network location to my Z drive.  This way any and all issues of LabVIEW referring to absolute paths goes away.  I do not develop in “offline” mode, I am always connected to one of my machines, whether it is by sitting directly in front of the machine or via a Remote Desktop Connection.  If you use a laptop, you could always split a piece off of your normal root partition and make a Z drive for yourself.

To do this yourself, create a network share and open it from Windows Explorer, and then select “Map Network Drive”.  This option will either be an icon or a menu option, and this all depends on the version of Windows that you are using.

So in my case, I have:

\\192.168.0.x\RAID-1 mapped to Z:\

So I work from:


More Code Posted to Github

So I have figured out how to use the MicroBlaze Core with an AXI-Stream FIFO, and I have also figured out how to export a project from Vivado by using the Vivado “Write Project TCL” option.

See the following project:

You have to re-generate the Vivado Project and create a new SDK workspace in order to get this to work on your machine.

How to regenerate a Vivado project from a TCL script:

Step 1 – Start Vivado

Step 2 – Change directory to where tcl script is located

Make sure you escape all Windows backslashes with another backslash




cd “Z:\\work\\git\\LabVIEW_Fpga\\06_MicroBlaze\\04_lwIP_Ex\\lwIP_Ex”

Step 3 – Source the tcl script

source init.tcl

That’s it!

Note: I am still in the process of converting all of my projects to use this method, if you want a quick taste, check out the project here:

Hello FPGA

So I want to use an FPGA.  I don’t want to spend thousands of hours reading through manuals, learning VHDL or the “easier” Verilog, and I don’t want to spend forever picking the right hardware, accessories, boards, installing drivers, getting it to work with my operating system…etc

I heard LabVIEW for FPGA is a great tool for FPGAs, but all of my computer programmer friends told me that LabVIEW sucks.  Then I started using LabVIEW for FPGA and realized that they were all wrong and I was right.

Everywhere I look, I see Wall Street people using FPGAs to process Network data before it goes in and out of the network.  In fact many solutions claim to have implemented portions of the network stack inside the FPGA, some even claim an entire TCP/IP stack.  One of these solutions is an open-source project called “NetFPGA”.  Now they have a 10 gigabit board, and a bunch of other similar products, but I don’t know what they are talking about by looking at their website, and I don’t have the time to listen to a bunch of long and boring YouTube videos.  I bought their 1 Gigabit board several years ago, and I was never able to get anything useful done with it.  From not having the right version of the Xilinx tools installed on my machine, lack of the IP Cores to just  not knowing all of the things that “every” programmer is “assumed” to know.  Anyway, go here and see what I mean:

Perhaps I am a moron, perhaps I suck at programming.  But at least I was able to use LabVIEW for FPGA to do some pretty interesting stuff many years ago.  Anyway, welcome to this blog where I will work towards the goal of making a 10 gigabit FPGA accelerated network card that can parse FIX messages and generate Fill Orders whenever certain conditions are met. I will use my own desktop computer for this, which is an older Windows machine with a 10 gigabit network card – Mellanox MNPA19-XTR ($24 USD) purchased for the purposes of this project, and a Windows machine that will be controlling the National Instruments PXIe-6592R ($10,999 USD) FPGA board.  I will install a MicroBlaze Soft Core Processor on the PXIe FPGA board to do the network connectivity for me and to run a simple C++ program that will instruct the rest of the FPGA on what to do.

This should not be difficult, this should not be tedious, and everything that I do I will log here, no more paper logs for me, no more confidentiality or secrecy or fear that someone out there will “steal” my ideas.  The truth is that everybody who is using FPGAs and is not using LabVIEW is making a mistake, and this blog will set out to help people to avoid making the mistakes already being made.  For the good of the world, for the good of Science, for the good of organic farming, for the good of small researchers who can’t afford to develop FPGA solutions using Verilog and VHDL.