Home – Backup – Dec

LabVIEW FPGA has an IP Export tool that you can use to bring vi’s from LabVIEW in to your custom design in Vivado.  One constraint is that you can only use LabVIEW FPGA primitives, or put another way – logic that stays inside the FPGA, meaning you cannot write to DRAM or access some other IO pins on the NI board you are developing your LabVIEW FPGA IP for. The other constraint is that the FPGA that your LabVIEW FPGA project lives in has to be of the same family as the board you intend to bring the IP to. … Read more

I normally do not like the idea of New Years Resolutions as I think that every day is Day One of any plan, not January 1st of the next year.  But it just so coincides that I have freed up some time to be able to spend more time on FPGANow.com again.  So I went ahead and removed the menus at the top and simplified this site with just an about and a home/blog page. I will look into re-adding all the Pages back but with updated /  better versions of each.  Otherwise, here is a list of things I … Read more

Part 4 of the Smart FPGA Nic, dealing with the OrderBook has been published. Go here to see more: https://fpganow.com/index.php/part-4-order-book/ Related source code: https://github.com/fpganow/arty_bats/tree/main/labview/arty/orderbook As I make updates to the code, mainly to make it prettier and easier for others to follow, I will make new a post for each change detailing all changes.  

I just created a ‘Page’ as opposed to a WordPress ‘Post’ documenting how I was able to parse BATS Market Data messages. This new style or format will be much better than my writing multiples posts.  Easier for the reader to find, and easier for me to find and to update an article. Anyway, look above, under the “SMART ‘FPGA-NIC’” menu above to find Part 2: Parse BATS Messages in an FPGA. (I never made a Page for Part 1, but I did implement everything required for it – Part 1 is supposed to be about Parsing UDP/IP in an … Read more

Related Source Repository: https://github.com/fpganow/vivado_scm Xilinx Vivado does not come with built-in source control.  If you are a Visual Studio user, or a IntelliJ IDEA or eclipse user, you may be familiar with using some sort of IDE-related source code control. Vivado has a different paradigm for source control: Export commands to re-generate the project as a tcl script. Add tcl and all related files to source-control After I tried following a lot of guides that I found on the internet for using source control, I was only successful after I did the following: Create a branch new project in folder … Read more

So my workflow is as follows: Create IP in NI LabVIEW FPGA Export via FPGA IP Export Tool Creates a VHDL wrapper (.vhd) Places IP in Design Checkpoint (.dcp) file Open my Vivado Block Design Use or update the VHDL wrapper that uses the Design Checkpoint Synthesis, Implementation, and Run The NI LabVIEW FPGA IP Export utility provides you with 2 files, a design checkpoint and a wrapper file to use for instantiating your IP using VHDL. A wrapper file is a very simple vhdl file, it contains the following interface to your design: entity NiFpgaIPWrapper_fpga_top isport (      … Read more

I got something working – with live hardware plugged in to my network. I used the larger version of the Arty Artix-7 board, which cost $250 USD, and made my own custom reader for the LabVIEW FPGA Network library.  I did not implement network writing features, nor do anything with the payload.  Nevertheless, this is a Proof-of-Concept and can be used to make a nice FPGA accelerated network application. Anyway, follow these instructions if you are Savvy enough with LabVIEW and you can examine the code. But first, a crude diagram of what is going on: Hardware used: Arty A7: … Read more

So I am dealing with the following scenarios: Scenario 1 – Genesys Zynq with SYZYGY SFP I have the Genesys Zynq UltraScale+ MPSoC 3EG board that does not provide direct access to the PHY pins, but has a SYZYGY port that I have plugged in to the SZG-DUALSFP module with an SFP connector. Scenario 2 – Arty A7 Artix-7 with 10/100 Mbit PHY I have the Arty A7 Artx-7 FPGA Development Board that gives me direct access to the pins of a 10/100 Mbit PHY. All I want to do is connect directly to a PHY so I can implement … Read more

Here is the new plan: Step 1 – Create a design using a MicroBlaze processing system, enable a UART connection and listen on an AXI FIFO and dump packets to the screen as they are received in chunks of X bytes. Step 2 – Insert some LabVIEW FPGA code to send one packet of data every second. Step 3 – Replace this LabVIEW FPGA code to listen to the MII Ethernet interface pins and to dump some data to the screen as before. Step 4 – Insert the LabVIEW FPGA UDP/IP library that is included with LabVIEW Now if you … Read more

I no longer have to look into figuring out how to code up or wire up the SZG-DUALSFP daughter board to the Digilent Genesys Zynq UltraScale MPSoC+ board. Why? Because I have a really old board that cost only $99 dollars that gives me direct access to the pins of an old 10/100 MBit PHY! That’s the Arty Artix-35T mini board! Anyway… I found a corresponding NI “no longer national instruments” board that targets the same family of FPGAs so I can get started. What that means is: Create a LabVIEW FPGA project that targets the CompactRIO 9053 board Use … Read more

So I spent some time to rebuild the out-of-box demo for the Genesys Zynq UltraScale MPSoC+ board.  Not everything worked for me right away, so I made this post to include all the things I did to get it to work.: My system: Windows 10 Windows Subsystem for Linux 2 Ubuntu 18.04 (<= Ubuntu 20 does not work unless you make a lot of changes) References: Schematics https://reference.digilentinc.com/_media/reference/programmable-logic/genesys-zu/genesys_zu-3eg_sch_public.pdf Official Documentation from Digilent Official Getting Started Guide on Digilent website https://reference.digilentinc.com/reference/programmable-logic/genesys-zu/getting-started https://reference.digilentinc.com/reference/programmable-logic/genesys-zu/start Genesys Zynq UltraScale MPSoC+ Reference Manual https://reference.digilentinc.com/reference/programmable-logic/genesys-zu/reference-manual Purchase Link https://store.digilentinc.com/genesys-zu-zynq-ultrascale-mpsoc-development-board/ PetaLinux Tools Documentation https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug1144-petalinux-tools-reference-guide.pdf Processing System 7 v5.,5 Documentation … Read more

I went to the Opal Kelly website again and noticed that there are a lot of menu options that I previously did not notice at the top menu. I found a sample board that uses their SZG-DUALSFP board: https://opalkelly.com/products/xem7320/ So now I can read the documentation for this board and be on my way! I also had some fun reading the specification documents for the SYZYGY specification, the SZG-DUALSFP board, and for the Finisar Tranceiver (Model #FTLF8524P2BNV) And I also discovered a Community Forum as well, where I could post any questions as well as any of my findings: https://forums.opalkelly.com/ … Read more

So I have the Genesys Zynq UltraScale + MPSoC board, I bought the SZG-DUALSFP from Opel Kelly, and I want to figure out how to wire this thing up. What pin goes where? I dunno.  I spent some time reading the SFP+ specification.  Everything makes sense.  Then I read through the SYZYGY specification.  Again, things make sense. So what does the interface look like? Anybody know? One though is to look at a sample from a similar board that uses an FMC based SFP connector. And then I was reminded of the book “How Would You Move Mount Fuji” – … Read more

After my previous post showing how to use the NI LabVIEW FPGA IP Export Utility to run LabVIEW FPGA code on a Zynqberry (http://fpganow.com/index.php/2020/09/28/zynqberry-with-breakout-board-and-labview/), I continued following the examples I could find on the internet and was able to connect to the board by using the PS (Processing System) built-int UART, and to communicate to the GPIO by using C code. Then I wanted to access the PHY or the ETH pins directly and to map them to some LabVIEW IP have that can function as an Ethernet MAC with some IP and UDP/TCP processing. After stumbling upon this post … Read more

Source Code: https://github.com/fpganow/Blink_LEDS Introduction There is a saying out there that goes ‘what are you going to do with an FPGA, blink a bunch of LEDs?’ Well… that saying is true.  Today I purchased a breakout board for the Zynberry and found an excellent guide on how to do just that: https://svenssonjoel.github.io/writing/blinkledzynq.pdf But I am different and I am going to do more than just ‘blink a bunch of LEDs’.  I am going to do something useful.  <= It’s a joke… hahaha… Okay, not only am I going to blink a bunch of LEDs by using an FPGA, I am … Read more

So I followed the Zynqberry tutorial here: https://www.knitronics.com/the-zynqberry-patch/getting-started-with-the-zynqberry-in-vivado-2018-2 And was able to get a basic Xilinx SDK application working on my Zynqberry, but with a twist… I used the NI LabVIEW IP Export tool to incorporate some LabVIEW code.  For now a simple adder that just adds 2 8-bit unsigned integers and outputs a 16-bit unsigned integer. Anyway, the key takeaways are: Follow the tutorial exactly and re-read it in case you have any confusion Wrap up the default block design using my wrapper

For those unfamiliar with the FIX protocol, see: https://en.wikipedia.org/wiki/Financial_Information_eXchange https://www.fixtrading.org/ The FIX Protocol transfers data uncompressed and in ASCII form.  The following data types are transferred like so: Integer Value To send the Integer 1,423, the TCP stream would look like this: Index ASCII Hex 0 ‘1’ 0x31 1 ‘4’ 0x34 2 ‘2’ 0x32 3 ‘3’ 0x33 Date Time Value To send the Date Time value pair “June 4th, 1998 2:58:48 PM”, the TCP stream would look like this: Index ASCII Hex 0 ‘1’ 0x31 1 ‘9’ 0x39 2 ‘9’ 0x39 3 ‘8’ 0x38 4 ‘0’ 0x30 5 ‘6’ 0x36 … Read more

[Updated]: It turns out there are 2 editions of this board, and it looks like the premium one with a 10 Gigabit SFP+ connector is not yet available in the USA.  However, I did some research and the lesser version of this board – the 3EV – has a SYZYGY connector, which supports SFP+ peripherals. So I ordered these 2 accessories and am awaiting a response from the manufacturer in case they actually do have one of the premium boards available: https://opalkelly.com/products/szg-dualsfp/ ($79.95) https://www.radwell.com/en-US/Buy/FINISAR/FINISAR/FTLF8524P2BNV ($27.28) If you have a bigger budget than that of a hobbyist, or are a hobbyist … Read more

I did some research looking for existing TCP/IP FPGA Cores.  There are two basic types – 10 Gigabit and non-10 Gigabit.  There is also a range of free and commercial solutions out there, and I’m sure the usual caveats apply.  Free = no documentation or support, Commercial = super expensive.  Anyway, here is what I discovered: The most important thing is that data comes in using an AXI4-Lite or similar interface.  What is an AXI4-Lite interface? Here is the official Xilinx documentation: https://www.xilinx.com/products/intellectual-property/axi_lite_ipif.html You can also simply think of it like this, on each clock cycle your FPGA reads the … Read more

I stumbled upon a board called the “Zynqberry” which is supposed to mimic a Raspberry Pi but with a Xilinx Zyn-7000 FPGA board present. This board aims to be an FPGA-enabled version of the Raspberry Pi and comes with a 100MBit connector.  Unfortunately it does not support 10 Gigabit.  I mean, how could it with such a small footprint? Anyway, this board will be perfect for me to demonstrate certain things that will make FPGA programming accessible to a hobbyist not willing to shell out thousands of dollars and to a student on a limited budget. Here is a link … Read more

If you are more of a hobbyist or doing this on the side, here are some possible board configurations that you can use to experiment with a 10 Gigabit connection. Remember, a SFP+ connection is synonymous with a 10 Gigabit connection. Zynq ZedBoard Zynq-7000 ARM/FPGA SoC Development Board If you are a student, you can apply for a free one through the Xilinx University Program. FPGA: Zynq-7000 AP SoC XC7Z020-CLG484 $449.00 https://store.digilentinc.com/zedboard-zynq-7000-arm-fpga-soc-development-board/ Genesis ZU: Zynq Ultrascale+ MPSoC Development Board Has 1 SFP+ Connector suitable for a 10 Gigabit connection. FPGA: Zynq Ultrascale+ (XCZU3EG-SFVC784-1-E) Pros: You can put the board on … Read more

Now you can run LabVIEW FPGA on the hardware of your choice with the new “LabVIEW FPGA IP Export Utility”.  That sounds great, but what’s that got to do with me? (quoting Rambo 3) Step 1 – Pick a non-National Instruments FPGA Board You will have to pick a non-National Instruments FPGA board that has an FPGA that uses Vivado (7 Series devices and above) and has a corresponding LabVIEW FPGA board that uses a device of the same family.  What does same family mean? Well, a Virtex-7 chip such as the VX485T has the same family as the VX690T. … Read more

Okay, so what now? For starters, you should know that LabVIEW 2020 FPGA uses Vivado 2019.1. And we are going to start with the currently available version/mode – IP Export to Netlist.  (The Source Code option requires you to email them to get it unlocked) What does this mean? It means that you can only use this utility on FPGAs that are in the Xilinx 7 Series or above.  This means: Virtex-7 Kintex-7 Kintex-Ultrascale Zynq-7000 Artix-7 (I do not know of any National Instruments boards that use this family) See AR#53109 on Xilinx.com: https://www.xilinx.com/support/answers/53109.html After installing this utility, you can find … Read more

Going to investigate what will be the biggest game changer for LabVIEW, FPGA’s and you. Okay, so the National Instruments website (http://www.ni.com) is pretty hard to navigate.  I somehow saw the following under the ‘RELATED PRODUCTS’ section on some page that I have since been unable to find: Then I was finally told by my brother to just search for it. Here is the direct link: https://www.ni.com/en-us/support/downloads/software-products/download.labview-fpga-ip-export-utility.html#345666 Here is the online version of the readme: http://www.ni.com/pdf/manuals/378241a.html And please note… the description clearly says ‘export’ … ‘third-party hardware’.  This means we can take all of my strategies and knowledge for using … Read more

When it comes down to your business identity, consistency is a key. Lorem ipsum dolor sit amet, consectetur adipiscing elit, sed do eiusmod tempor incididunt ut labore et dolore magna aliqua. Ut placerat orci nulla pellentesque dignissim enim sit amet venenatis eget velit aliquet satis id consectetur purus. Pretium fusce id velit ut tortor pretium viverra suspendisse. Sed augue lacus viverra vitae congue eu consequent. Id donec ultrices tincidunt arcu. Dolor sit amet consectetur adipiscing elit pellentesque habitant morbi. Lectus nulla at volutpat diam. Elementum curabitur vitae nunc sed velit dignissim sodales ut eu. At imperdiet dui accumsan sit amet … Read more

When it comes down to your business identity, consistency is a key. Lorem ipsum dolor sit amet, consectetur adipiscing elit, sed do eiusmod tempor incididunt ut labore et dolore magna aliqua. Ut placerat orci nulla pellentesque dignissim enim sit amet venenatis eget velit aliquet satis id consectetur purus. Pretium fusce id velit ut tortor pretium viverra suspendisse. Sed augue lacus viverra vitae congue eu consequent. Id donec ultrices tincidunt arcu. Dolor sit amet consectetur adipiscing elit pellentesque habitant morbi. Lectus nulla at volutpat diam. Elementum curabitur vitae nunc sed velit dignissim sodales ut eu. At imperdiet dui accumsan sit amet … Read more

When it comes down to your business identity, consistency is a key. Lorem ipsum dolor sit amet, consectetur adipiscing elit, sed do eiusmod tempor incididunt ut labore et dolore magna aliqua. Ut placerat orci nulla pellentesque dignissim enim sit amet venenatis eget velit aliquet satis id consectetur purus. Pretium fusce id velit ut tortor pretium viverra suspendisse. Sed augue lacus viverra vitae congue eu consequent. Id donec ultrices tincidunt arcu. Dolor sit amet consectetur adipiscing elit pellentesque habitant morbi. Lectus nulla at volutpat diam. Elementum curabitur vitae nunc sed velit dignissim sodales ut eu. At imperdiet dui accumsan sit amet … Read more

When it comes down to your business identity, consistency is a key. Lorem ipsum dolor sit amet, consectetur adipiscing elit, sed do eiusmod tempor incididunt ut labore et dolore magna aliqua. Ut placerat orci nulla pellentesque dignissim enim sit amet venenatis eget velit aliquet satis id consectetur purus. Pretium fusce id velit ut tortor pretium viverra suspendisse. Sed augue lacus viverra vitae congue eu consequent. Id donec ultrices tincidunt arcu. Dolor sit amet consectetur adipiscing elit pellentesque habitant morbi. Lectus nulla at volutpat diam. Elementum curabitur vitae nunc sed velit dignissim sodales ut eu. At imperdiet dui accumsan sit amet … Read more

So with the Coronavirus, the markets have been seeing increased volatility, and all the high frequency traders are making a lot of money, or losing a lot of money… I scrolled through the list of repositories on the fpganow github org and found a relevant project that deals with the parsing of market data only – without any regard to the TCP/IP portion. I will resurrect this repo and see what needs to be done in order to use it. Now… if you are an HFT person, I recommend you look into LabVIEW FPGA, because sooner or later you will … Read more

I received an email from a reader asking me what controller I am using, so I figure I would make a new post with this information: (All links open in a new tab) PXIe-8105 Embedded Controller https://www.ni.com/en-us/support/model.pxie-8105.html PXIe-1062Q https://www.ni.com/en-us/support/model.pxie-1062q.html PXIe-6592R https://www.ni.com/en-us/support/model.pxie-6592.html And a picture (why not?):  

So first off, I have merged my code to master, see it here: https://github.com/fpganow/MicroBlaze_lwIP And while I work on updating the README.md file, here are 2 slides for you to look at: So, if you have the appropriate NI hardware, you can clone down this repository and run 1 TCP and 1 UDP session to your FPGA! Do you have an existing FPGA solution? If you follow the Vivado Project that is exported from LabVIEW FPGA, you can probably import your existing FPGA solution to National Instruments hardware, plug in the lwip TCP/IP code that I have running on a … Read more

As I was traversing my mental decision tree using a depth-first search model of digger deeper and deeper in to the lwip TCP/IP source code, I thought to myself that I should go back up the decision tree and take a deeper look at the tcpdump output. It turns out I was setting the source and destination IP addresses to the same value. Once I set the source IP address to NULL, the TCP/IP stack auto-binded it to the IP address of the MAC and all communications started working. Now I will do some code cleanup, will push to github … Read more

What I have working right now: A UDP packet enters the FPGA via the 10 Gigabit PHY that is connected to the FPGA. The 10 Gigabit Ethernet MAC running on the FPGA consumes the Ethernet Frame and passes it in to a c++ application running inside the MicroBlaze Processor. The MicroBlaze Processor is running a version of the open-source TCP/IP stack “lwip” which processes the UDP datagram, extracts the pertinent information and passes this information to a specific callback function that is implemented by the user. In this case that would be me. My implementation of this callback function sends … Read more

The National Instruments “LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2 – Linux” is only officially supported on Red Hat Enterprise Linux and CentOS. CentOS is basically a clone of Red Hat Enterprise Linux, also known as RHEL. I like to joke and call it R-HELL. The reason is valid, Red Hat Enterprise Linux has a longer release cycle, which means that a new package won’t just show up and break a lot of your code, or more importantly will not introduce Security Flaws in to your system just because you ran a system update. But what about … Read more

So it appears to me that Monero/CryptoNote mining has gained a lot of popularity lately, and this has led many people to this website.  Let me note that LabVIEW FPGA is a proprietary tool that comes with a 30-day Evaluation.  After that, you have to spin up a new virtual machine and reinstall LabVIEW to keep your installation alive.  However, when it comes to FPGA development, LabVIEW is the best tool out there. Sure, it may not support the latest board from Xilinx or Digilent or whoever, but what it does support it supports well. Take the PXIe-6592 board.  I … Read more

So after some serious debugging, editing, and regenerating of the bitstream, I was able to send out an ARP response from the FPGA to my linux server, and for my linux server to send a UDP packet in to the MicroBlaze.  This was all verified via UART debug statements. Now while I work on cleaning this all up, you can actually use this code in your project, but only if you have enough knowledge of LabVIEW and Xilinx.  My job is to help bridge that gap, but for now: The source code is located in: https://github.com/fpganow/MicroBlaze_lwIP The application that is … Read more

Working from scratch, I created a LabVIEW FPGA project that imports a MicroBlaze design that communicates with LabVIEW via a UART, and has the ability to change the elf file in a much shorter time frame than before. I did this by adding the MicroBlaze to the project after it had been exported to Vivado, and not from within the CLIP that is imported as before.  The only bad news is that I have to synthesize the FPGA project from Vivado, which currently is not connected to the NI FPGA Compile Cloud.  This may be a feature that is coming … Read more

Before I go any further and start wiring up my code to use the lwIP on the embedded MicroBlaze, I will need some sort of better method of debugging.  All code that I have implemented that uses a MicroBlaze processor via the Xilinx tools makes use of the UART to send and receive standard input and output. Right now I have been getting around this by writing values to the GPIO and to the host via a FIFO, but I do not want to have to recompile all of my code and move where I have wired the FIFO to … Read more

If you purchase the National Instruments PXIe-6592R Board, retailing at $12,197.00 USD, I guarantee that you can run an FPGA accelerated 10 Gigabit network card in as much time as it takes for you to synthesize your code!  Call Now, the number is 1-900-XXX-YYYY. Batteries not included, strings attached.  But seriously, I have just cleaned up the code and was able to run this from its new home, namely a brand new directory inside my kitchen sink of LabVIEW samples. Download the source code and take a look at it here: https://github.com/JohnStratoudakis/LabVIEW_Fpga/tree/master/07_10_Gigabit/02_FPGANic You can take a look at the MicroBlaze … Read more

I normally avoid shop words or “corporate speak” because I feel it dehumanizes us, but sometimes these phrases are necessary.  So here is the “30,000 foot” view.  And please pardon the appearance of my flow charts and diagrams, I am not a graphic designer… All images open in a new tab, so just click on them with ease until I figure out how to make this WordPress theme wider. Take  look at this: There are four (4) 10 Gigabit ports available on this device, but I am using only one of them for this design. The FPGA design contains a … Read more

I have wired up the components of my 10 Gigabit FPGA Accelerated Network card with great care, and I decided to have my “tester” application skip the lwIP stack and to pass the received packet directly to the host for testing/verification purposes. Everything was checking out fine, the LabVIEW code looked flawless, the interface to the 10 Gigabit Transceiver was perfect.  All looked fine, but for some reason I was not receiving the packets on the host. I analyzed the code, inserted probes and what not.  And finally, I was reading through the actual C++ code (MicroBlaze C++ that is) … Read more

The 10 Gigabit MAC/transceiver gives me 64 bit data words.  I currently think I am giving and getting  64 bit data words, but I am really only using 32 bits.  I came to this conclusion after I tried reading a 64 bit word and saw the data was simply two repeated 32 bit words.  Additionally some random person on the internet said that the MicroBlaze data bus is 32-bit and you have to use some sort of data width converter ip. Out of luck… I don’t know how to use the converter, but I am sure there is a way … Read more

I wired up the 10 gigabit ethernet MAC to my MicroBlaze instance to my host computer and compiled/synthesized everything.  I then turn on my “quiet” PXIe-1062Q and fire up my tester application and it did not work…  I open up an isolated tester – “Fpga-Mac-Top.vi”, and it worked.  I open up the isolated MicroBlaze tester – “Fpga-MicroBlaze-Top.vi”, and nothing.  Not even a read from the GPIO. This is quite strange… why is it not working? I spend some time looking over everything, re-generating output products, synthesizing from Vivado, bringing the design back in to LabVIEW, and long story short I … Read more

Ever since I started developing this LabVIEW FPGA project that uses a MicroBlaze soft processor to process TCP streams, I have learned a lot and can comment on the pros and cons of using LabVIEW FPGA vs using a traditional Xilinx/Altera based FPGA development approach. For starters, LabVIEW FPGA blows every single other FPGA development system out of the water when it comes to developing prototypes.  I made a prototype for implementing a Monero miner in record time.  I don’t remember how long it took, but you can see my commit history here: https://github.com/JohnStratoudakis/CryptoCurrencies Then I was able to implement a … Read more

So here is the most simple, FPGA-based Network Interface Card that I know of. This application will start Port 0 of the 10 Gigabit Network interface that is provided by the PXIe-6592R (http://www.ni.com/en-us/support/model.pxie-6592.html) board by National Instruments, and will allow you to do any of the following: Check if any new ethernet frames have been received, and display the information, including the raw bytes of any such received frame Send a raw ethernet frame out of Port 0 I have included the necessary code to parse and generate the following types of packets, enabling you to communicate with another computer on your … Read more

I finished writing an application that exercises the first Port of the 10 Gigabit Ethernet Interface that is provided with the National Instruments PXIe-6592R board and as I started taking manual screenshots via the LabVIEW “File->Print” option I began to ponder, can this be done more easily? Or dare I say it “programmatically”? The LabVIEW Report Generation Palette has a VI named “Easy Print VI Panel and Documentation”.  In addition to the plethora of options, this VI also is hard to use and proved to be unstable for my purposes.  If you want to try it in your application, see … Read more

I am getting real close to finishing my proof-of-concept FPGA-based network card that is based on the PXIe-6592 National Instruments Board which uses the Kinex-7 410t FPGA chip by Xilinx, and has 2GB of DDR3 RAM. Using the Arty Arix board, I was able to make sure that the MicroBlaze code running the lwIP TCP/IP stack works fine, and I was able to use a NI example to make the 10 Gigabit Ethernet MAC part.  Only issue is that the NI code is quite complex and uses features and ideas that I have never seen before. Nevertheless, I am iterating … Read more

What is the product of 0x9D0BF6FDAC70AB52 and 0x6408F6540A1384CB?  Well, according to LabVIEW for Windows, the answer is 0x2D90DE07C0C42206.  According to C++ on OSX (without any optimizations, usage of Intel Intrinsic functions), the answer is also 0x2D90DE07C0C42206. The real answer is…  0x3D5E2BF7DCBCA6622D90DE07C0C42206. How do you get this number? You have to use compiler intrinsics, or calculate this value yourself.  LabVIEW does not make it easy to call an Intel Compiler intrinsic, so I took it upon myself to implement this myself.  Here is a screenshot of the implementation in LabVIEW for Windows: To download and use this code in your project, see: https://github.com/JohnStratoudakis/CryptoCurrencies/blob/master/Monero/lv-monero/CryptoNight-Step-3/Host-Implementation/Step-3-Multiply-U64.vi … Read more

So I wanted to implement a simple, stripped down version of the open-source lightweight IP stack “lwIP” (https://savannah.nongnu.org/projects/lwip/) inside my LabVIEW FPGA project that I can handle TCP and UDP data streams. I do not have a lot of experience with this, and I found that building such a project inside Vivado would take around 3 hours to simulate with all of the source code of the lwIP project embedded in the elf file. I ended up purchasing a $99 board from Digilent that uses an Artix-7 35T board: https://www.xilinx.com/products/boards-and-kits/arty.html. On this board I was able to run and debug … Read more

I spent some time analyzing the Monero CryptoCurrency source code to understand the algorithm, how it works and to see if it is doable with an FPGA via LabVIEW for FPGA, our secret weapon. I learned that there are 4 steps to the Monero “CryptoNight” algorithm and that step 3 is the part that does the heavy lifting, with around 500k reads and writes to a small section of memory that is 2 megabytes in size.  This section of memory was specifically selected to be a size that coincides with the size of most processor Level 3 caches.  This is … Read more

So I wanted to mention that I have all of my LabVIEW (and Vivado) code saved on a RAID-1 mirrored location on my network.  From each of my workstations, I map the same network location to my Z drive.  This way any and all issues of LabVIEW referring to absolute paths goes away.  I do not develop in “offline” mode, I am always connected to one of my machines, whether it is by sitting directly in front of the machine or via a Remote Desktop Connection.  If you use a laptop, you could always split a piece off of your … Read more

So I have figured out how to use the MicroBlaze Core with an AXI-Stream FIFO, and I have also figured out how to export a project from Vivado by using the Vivado “Write Project TCL” option. See the following project: https://github.com/JohnStratoudakis/LabVIEW_Fpga/tree/master/06_MicroBlaze/04_lwIP_Ex You have to re-generate the Vivado Project and create a new SDK workspace in order to get this to work on your machine. How to regenerate a Vivado project from a TCL script: Step 1 – Start Vivado Step 2 – Change directory to where tcl script is located Make sure you escape all Windows backslashes with another backslash … Read more

I just uploaded some code to GitHub that is a full demonstration on how to use LabVIEW FPGA 2017, the MicroBlaze MCS core and the IO Bus that is attached to the MicroBlaze MCS. Clone the following repository: https://github.com/JohnStratoudakis/LabVIEW_Fpga/tree/master/05_MicroBlaze_Mcs/02_MicroBlaze_Mcs_IO_Bus and open the LabVIEW project: https://github.com/JohnStratoudakis/LabVIEW_Fpga/blob/master/05_MicroBlaze_Mcs/02_MicroBlaze_Mcs_IO_Bus/02_MicroBlaze_Mcs_IO_Bus.lvproj Look at the Vivado 2015.4 project: https://github.com/JohnStratoudakis/LabVIEW_Fpga/blob/master/05_MicroBlaze_Mcs/02_MicroBlaze_Mcs_IO_Bus/MicroBlaze_Mcs_IO_Bus/MicroBlaze_Mcs_IO_Bus.xpr And finally, using the Xilinx SDK set your workspace to: https://github.com/JohnStratoudakis/LabVIEW_Fpga/tree/master/05_MicroBlaze_Mcs/02_MicroBlaze_Mcs_IO_Bus/MicroBlaze_Mcs_IO_Bus/MicroBlaze_Mcs_IO_Bus.sdk Now if you do not have access to LabVIEW from your current machine, I have included a screen shot for each VI with the words “Front” or “Back” added to the filename, and in the case where … Read more

The MicroBlaze Micro Controller Syste (MCS) is a soft-core processor that can be customized and placed inside the fabric of your FPGA.  The uses of this are limitless. Requirements: LabVIEW 2017 http://www.ni.com/download/labview-development-system-2017/6679/en/ LabVIEW 2017 FPGA Module http://www.ni.com/download/labview-fpga-module-2017/6635/en/ LabVIEW 2017 FPGA Module Xilinx Compilation Tools for Vivado 2015.4 http://www.ni.com/download/labview-fpga-module-2017/6634/en/ Xilinx Software Development Kit version 2015.4 https://www.xilinx.com/products/design-tools/embedded-software/sdk.html Source Code Browse the source code online via github by visiting the following link: https://github.com/JohnStratoudakis/LabVIEW_Fpga/tree/master/05_MicroBlaze_Mcs/01_MicroBlaze_Mcs_GPIO To download the source code, clone the entire repository with: git clone git@github.com:JohnStratoudakis/LabVIEW_Fpga.git You can also download a zip file with the entire repository: https://github.com/JohnStratoudakis/LabVIEW_Fpga/archive/master.zip What this Guide Accomplishes This … Read more

Filter Market Data Messages in an FPGA – part 3 Note: Skip directly to GitHub.com to download the source code by following this link: https://github.com/fpganow/MarketData System Requirements: LabVIEW 2016 LabVIEW 2016 FPGA Module http://www.ni.com/labview/ This post will cover the next iteration of implementing an OrderBook inside an FPGA that is based on a NASDAQ ITCH 4.1 market data feed. Some time has passed and I have finally found enough time to finish all the code changes required for the two (2) components listed below, along with the requisite test harnesses to validate. Starting off, here are the components of an … Read more

Skip directly to the source code on Github.com here: https://github.com/JohnStratoudakis/LabVIEW_Fpga/tree/master/MarketData/MarketData_01 So what now.  We know what a NASDAQ ITCH 4.1 Market Data Message looks like.  The format is very simple, there is some – yes – ASCII data in the message format, and all messages are preceded by the message length.  Message length preceding the message makes it very easy to interpret a feed from inside an FPGA. What to do first? Well, what does eXtreme Programming say to do? It says keep it simple. So, I am working on a LabVIEW 2016 program that does the following: Open a … Read more

So I went to NASDAQs ftp site and downloaded the entire ITCH feed for November 9th, 2013.  The file was large – 319MB compressed, and you can download it yourself from here: ftp://emi.nasdaq.com/ITCH/11092013.NASDAQ_ITCH41.gz. NASDAQ has a very simple document describing the specification here: http://nasdaqtrader.com/content/technicalsupport/specifications/dataproducts/NQTV-ITCH-V4_1.pdf I skimmed over the specification to get an idea of how Market Data works.  What I basically understand is that at the start of the trading day, NASDAQ sends a list of all securities that will be available to trade for that day following by a bunch of messages indicating changes to prices being offered to buy … Read more

I am sure that every single trader gets nervous whenever Trump speaks.  If he says “wall” they have to go short the Mexican Peso, if he talks about Obamacare or the “Unaffordable Care Act”, they have to short Healthcare stocks.  During his first news conference on Thursday, January 11th, 2017, he went a step further and said he wants bidding and competition for Government purchases of Pharmaceutical drugs.  So not only did the Mexican Peso suffer, but so did Pharmaceutical companies such as GlaxoSmithKline, Merck and Pfizer, among others! His news conference was from 11:00 am to 12:15 pm. Here … Read more

So I want to use an FPGA.  I don’t want to spend thousands of hours reading through manuals, learning VHDL or the “easier” Verilog, and I don’t want to spend forever picking the right hardware, accessories, boards, installing drivers, getting it to work with my operating system…etc I heard LabVIEW for FPGA is a great tool for FPGAs, but all of my computer programmer friends told me that LabVIEW sucks.  Then I started using LabVIEW for FPGA and realized that they were all wrong and I was right. Everywhere I look, I see Wall Street people using FPGAs to process … Read more